From patchwork Mon Jun 13 23:04:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 9174697 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3633C60573 for ; Mon, 13 Jun 2016 23:10:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2645026861 for ; Mon, 13 Jun 2016 23:10:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 18C722723E; Mon, 13 Jun 2016 23:10:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7320126861 for ; Mon, 13 Jun 2016 23:10:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1423578AbcFMXJ7 (ORCPT ); Mon, 13 Jun 2016 19:09:59 -0400 Received: from mail-pa0-f44.google.com ([209.85.220.44]:33294 "EHLO mail-pa0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1423402AbcFMXEy (ORCPT ); Mon, 13 Jun 2016 19:04:54 -0400 Received: by mail-pa0-f44.google.com with SMTP id b13so27520719pat.0 for ; Mon, 13 Jun 2016 16:04:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GTajtZwsP4I5RyIYHEGusqjavNlsSga7UG0PuoPPmKg=; b=DhOmN2bcAmLdBSqvTZdkse+igB2NVC7cOiG65GhRAIKeSpzX8kAjxKjOL9P5F7grz0 9lnFj8U3o+VhesmTPcX40cY21ciA8HIRCC9x2c1Uhk8beniylUnvjuwXM6DGENtCxu7H bB4t8OnruvKNYBdZZwHf9skwyDquXLfKPxW68= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GTajtZwsP4I5RyIYHEGusqjavNlsSga7UG0PuoPPmKg=; b=X7J2ZYxJEX7WxE+2w4n7IMU4zsJQgim/Fe2JftvIrB9gRBsup/dP5cAe8V43aNQqUU zWwboOj1ms0yxHQ0HSV4S8kjJfDoOdiC/f481UajCFiimRYsveulZJAnIJnflwgwOtGh OXIl+nltATsVsjXvdQeVvDU3Os13E1CDrK4pRS5zRiiXJK5HmZmJEdEAe0A98hZj9g+6 jQpazL/DYscM99GrTWmLhUDeIpHIEyJOl4x5ENrtzn2/D3AhXqVBft3hz/bCUqTC9L5Q JbgyfT6G4+hN1KCUwMRCZ522B9oPjeJXjPt33+TPH8qLXO462xZsyWAIm0vZ1/e3xEpN XzEg== X-Gm-Message-State: ALyK8tK7dOdmm1Fv7wFJlb+JBMcG8uoX8vwGaZsAjme54z9/vECQRVWeBZujfKznwAkA4XGL X-Received: by 10.67.3.227 with SMTP id bz3mr24277453pad.67.1465859093799; Mon, 13 Jun 2016 16:04:53 -0700 (PDT) Received: from tictac.mtv.corp.google.com ([172.22.65.76]) by smtp.gmail.com with ESMTPSA id pk18sm8906434pab.27.2016.06.13.16.04.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 13 Jun 2016 16:04:52 -0700 (PDT) From: Douglas Anderson To: ulf.hansson@linaro.org, kishon@ti.com, Heiko Stuebner , robh+dt@kernel.org Cc: shawn.lin@rock-chips.com, xzy.xu@rock-chips.com, briannorris@chromium.org, adrian.hunter@intel.com, linux-rockchip@lists.infradead.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Douglas Anderson , pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 03/11] Documentation: mmc: sdhci-of-arasan: Add soc-ctl-syscon for corecfg regs Date: Mon, 13 Jun 2016 16:04:27 -0700 Message-Id: <1465859076-4868-4-git-send-email-dianders@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1465859076-4868-1-git-send-email-dianders@chromium.org> References: <1465859076-4868-1-git-send-email-dianders@chromium.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP As can be seen in Arasan's datasheet [1] there are several "corecfg" settings in their SDHCI IP Block that are supposed to be controlled by software. Although the datasheet referenced is a bit vague about how to access corecfg, in Figure 5 you can see that for Arasan's PHY (a separate component than their SDHCI component) they describe the "phyctrl" registers as being "FROM SOC CTL REG", implying that it's up to the licensee of the Arasan IP block to implement these registers. It seems sane to assume that the "corecfg" registers in their SDHCI IP block works in a similar way for all licensees of the IP Block. Device tree has a model that allows a device to get a reference to random registers located elsewhere in the SoC: sysctl. Let's leverage this model and allow adding a sysctl reference to access the control registers for the Arasan SDHCI PHYs. Having a reference to the control registers doesn't do much for us on its own since the Arasan spec doesn't specify how these corecfg values are laid out in memory. In the SDHCI driver we'll need a map detailing where each corecfg can be found in each implementation. This map can be found using the primary compatible string of the SDHCI device. In that spirit, document that existing rk3399 device trees already have a specific compatible string, though up to now they've always been relying on the driver supporting the generic. Note that since existing devices seem to work fairly well as-is, we'll list the syscon reference as "optional", but it's likely that we'll run into much fewer problems if we can actually set the proper values in the syscon, so it is strongly suggested that any SoCs where we have a map to set the corecfg also include a reference to the syscon. [1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf Signed-off-by: Douglas Anderson Acked-by: Rob Herring Reviewed-by: Shawn Lin Reviewed-by: Heiko Stuebner --- Changes in v2: - Clean up description of rk3399 PHY (Shawn) - Add Rob Herring's Ack. .../devicetree/bindings/mmc/arasan,sdhci.txt | 27 ++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt index 31b35c3a5e47..476604e6ce2a 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt @@ -9,8 +9,12 @@ Device Tree Bindings for the Arasan SDHCI Controller [4] Documentation/devicetree/bindings/phy/phy-bindings.txt Required Properties: - - compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or - 'arasan,sdhci-4.9a' or 'arasan,sdhci-5.1' + - compatible: Compatibility string. One of: + - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY + - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY + - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY + - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY + For this device it is strongly suggested to include arasan,soc-ctl-syscon. - reg: From mmc bindings: Register location and length. - clocks: From clock bindings: Handles to clock inputs. - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb" @@ -22,6 +26,11 @@ Required Properties for "arasan,sdhci-5.1": - phys: From PHY bindings: Phandle for the Generic PHY for arasan. - phy-names: MUST be "phy_arasan". +Optional Properties: + - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt) + used to access core corecfg registers. Offsets of registers in this + syscon are determined based on the main compatible string for the device. + Example: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; @@ -42,3 +51,17 @@ Example: phys = <&emmc_phy>; phy-names = "phy_arasan"; } ; + + sdhci: sdhci@fe330000 { + compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; + reg = <0x0 0xfe330000 0x0 0x10000>; + interrupts = ; + clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; + clock-names = "clk_xin", "clk_ahb"; + arasan,soc-ctl-syscon = <&grf>; + assigned-clocks = <&cru SCLK_EMMC>; + assigned-clock-rates = <200000000>; + phys = <&emmc_phy>; + phy-names = "phy_arasan"; + status = "disabled"; + };