From patchwork Thu Jun 16 13:23:27 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 9180851 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DDC6F60573 for ; Thu, 16 Jun 2016 13:38:19 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CD74027F07 for ; Thu, 16 Jun 2016 13:38:19 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C1AB32836B; Thu, 16 Jun 2016 13:38:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5C6BE27F07 for ; Thu, 16 Jun 2016 13:38:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754255AbcFPNho (ORCPT ); Thu, 16 Jun 2016 09:37:44 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:14163 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754662AbcFPNhX (ORCPT ); Thu, 16 Jun 2016 09:37:23 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Thu, 16 Jun 2016 06:37:04 -0700 Received: from HQHUB102.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Thu, 16 Jun 2016 06:33:46 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 16 Jun 2016 06:33:46 -0700 Received: from BGMAIL104.nvidia.com (10.25.59.13) by HQHUB102.nvidia.com (172.20.187.25) with Microsoft SMTP Server (TLS) id 8.3.406.0; Thu, 16 Jun 2016 06:37:21 -0700 Received: from HQMAIL104.nvidia.com (172.18.146.11) by bgmail104.nvidia.com (10.25.59.13) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Thu, 16 Jun 2016 13:37:17 +0000 Received: from ldewanganubuntu-System-Product-Name.nvidia.com (172.20.13.39) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Thu, 16 Jun 2016 13:37:13 +0000 From: Laxman Dewangan To: , , , , CC: , , , , , Laxman Dewangan , Javier Martinez Canillas Subject: [PATCH V2 4/4] clk: max77686: Add support for MAX77620 clocks Date: Thu, 16 Jun 2016 18:53:27 +0530 Message-ID: <1466083407-28793-5-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1466083407-28793-1-git-send-email-ldewangan@nvidia.com> References: <1466083407-28793-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Maxim Max77620 has one 32KHz clock output and the clock HW IP used on this PMIC is same as what it is there in the MAX77686. Add clock driver support for MAX77620 on the MAX77686 driver. Signed-off-by: Laxman Dewangan CC: Krzysztof Kozlowski CC: Javier Martinez Canillas Signed-off-by: Laxman Dewangan Tested-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Reviewed-by: Krzysztof Kozlowski --- Changes from V1: - Updated based on changes done in first patch. --- drivers/clk/Kconfig | 7 ++++--- drivers/clk/clk-max77686.c | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 6afad74..d75f4c5 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -32,10 +32,11 @@ config COMMON_CLK_WM831X source "drivers/clk/versatile/Kconfig" config COMMON_CLK_MAX77686 - tristate "Clock driver for Maxim 77686/77802 MFD" - depends on MFD_MAX77686 + tristate "Clock driver for Maxim 77686/77802/MAX77620 MFD" + depends on MFD_MAX77686 || MFD_MAX77620 ---help--- - This driver supports Maxim 77686/77802 crystal oscillator clock. + This driver supports Maxim 77686/77802/MAX77620 crystal oscillator + clock. config COMMON_CLK_RK808 tristate "Clock driver for RK808" diff --git a/drivers/clk/clk-max77686.c b/drivers/clk/clk-max77686.c index 9aba3a8..19f6208 100644 --- a/drivers/clk/clk-max77686.c +++ b/drivers/clk/clk-max77686.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -35,12 +36,14 @@ #include #include +#include #define MAX77802_CLOCK_LOW_JITTER_SHIFT 0x3 enum max77686_chip_name { CHIP_MAX77686, CHIP_MAX77802, + CHIP_MAX77620, }; struct max77686_hw_clk_info { @@ -97,6 +100,15 @@ max77686_hw_clk_info max77802_hw_clks_info[MAX77802_CLKS_NUM] = { }, }; +static const struct +max77686_hw_clk_info max77620_hw_clks_info[MAX77620_CLKS_NUM] = { + [MAX77620_CLK_32K_OUT0] = { + .name = "32khz_out0", + .clk_reg = MAX77620_REG_CNFG1_32K, + .clk_enable_mask = MAX77620_CNFG1_32K_OUT0_EN, + }, +}; + static struct max77686_clk_init_data *to_max77686_clk_init_data( struct clk_hw *hw) { @@ -181,6 +193,11 @@ static int max77686_clk_probe(struct platform_device *pdev) hw_clks = max77802_hw_clks_info; break; + case CHIP_MAX77620: + num_clks = MAX77620_CLKS_NUM; + hw_clks = max77620_hw_clks_info; + break; + default: dev_err(dev, "Unknown Chip ID\n"); return -EINVAL; @@ -284,6 +301,7 @@ static int max77686_clk_remove(struct platform_device *pdev) static const struct platform_device_id max77686_clk_id[] = { { "max77686-clk", .driver_data = CHIP_MAX77686, }, { "max77802-clk", .driver_data = CHIP_MAX77802, }, + { "max77620-clock", .driver_data = CHIP_MAX77620, }, {}, }; MODULE_DEVICE_TABLE(platform, max77686_clk_id);