From patchwork Mon Jun 27 14:04:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 9200681 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 625BD607D3 for ; Mon, 27 Jun 2016 14:05:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 53E5228591 for ; Mon, 27 Jun 2016 14:05:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 48F5E28595; Mon, 27 Jun 2016 14:05:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.2 required=2.0 tests=BAYES_00,HK_RANDOM_FROM, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F19B828591 for ; Mon, 27 Jun 2016 14:05:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B61406E2FB; Mon, 27 Jun 2016 14:05:49 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id EE68E6E2D3 for ; Mon, 27 Jun 2016 14:04:55 +0000 (UTC) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 27 Jun 2016 07:04:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.26,536,1459839600"; d="scan'208"; a="1005965195" Received: from tursulin-linux.isw.intel.com ([10.102.226.167]) by orsmga002.jf.intel.com with ESMTP; 27 Jun 2016 07:04:28 -0700 From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Mon, 27 Jun 2016 15:04:12 +0100 Message-Id: <1467036260-9252-6-git-send-email-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1467036260-9252-1-git-send-email-tvrtko.ursulin@linux.intel.com> References: <1467036260-9252-1-git-send-email-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [PATCH 05/13] drm/i915: Consolidate get/set_seqno X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/intel_ringbuffer.c | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 5dddcdd2570d..74967e84eed3 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -2877,6 +2877,8 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, struct intel_engine_cs *engine) { engine->write_tail = ring_write_tail; + engine->get_seqno = ring_get_seqno; + engine->set_seqno = ring_set_seqno; if (INTEL_GEN(dev_priv) >= 6) { engine->add_request = gen6_add_request; @@ -2940,8 +2942,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev) engine->add_request = gen8_render_add_request; engine->flush = gen8_render_ring_flush; engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; - engine->get_seqno = ring_get_seqno; - engine->set_seqno = ring_set_seqno; if (i915_semaphore_is_enabled(dev_priv)) { WARN_ON(!dev_priv->semaphore_obj); engine->semaphore.sync_to = gen8_ring_sync; @@ -2954,8 +2954,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev) if (IS_GEN6(dev_priv)) engine->flush = gen6_render_ring_flush; engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; - engine->get_seqno = ring_get_seqno; - engine->set_seqno = ring_set_seqno; if (i915_semaphore_is_enabled(dev_priv)) { engine->semaphore.sync_to = gen6_ring_sync; engine->semaphore.signal = gen6_signal; @@ -2989,8 +2987,6 @@ int intel_init_render_ring_buffer(struct drm_device *dev) engine->flush = gen2_render_ring_flush; else engine->flush = gen4_render_ring_flush; - engine->get_seqno = ring_get_seqno; - engine->set_seqno = ring_set_seqno; engine->irq_enable_mask = I915_USER_INTERRUPT; } @@ -3059,8 +3055,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) if (IS_GEN6(dev_priv)) engine->write_tail = gen6_bsd_ring_write_tail; engine->flush = gen6_bsd_ring_flush; - engine->get_seqno = ring_get_seqno; - engine->set_seqno = ring_set_seqno; if (INTEL_GEN(dev_priv) >= 8) { engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; @@ -3093,8 +3087,6 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev) } else { engine->mmio_base = BSD_RING_BASE; engine->flush = bsd_ring_flush; - engine->get_seqno = ring_get_seqno; - engine->set_seqno = ring_set_seqno; if (IS_GEN5(dev_priv)) { engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; } else { @@ -3124,8 +3116,6 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev) intel_ring_default_vfuncs(dev_priv, engine); engine->flush = gen6_bsd_ring_flush; - engine->get_seqno = ring_get_seqno; - engine->set_seqno = ring_set_seqno; engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; engine->dispatch_execbuffer = @@ -3154,8 +3144,6 @@ int intel_init_blt_ring_buffer(struct drm_device *dev) intel_ring_default_vfuncs(dev_priv, engine); engine->flush = gen6_ring_flush; - engine->get_seqno = ring_get_seqno; - engine->set_seqno = ring_set_seqno; if (INTEL_GEN(dev_priv) >= 8) { engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; @@ -3209,8 +3197,6 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev) intel_ring_default_vfuncs(dev_priv, engine); engine->flush = gen6_ring_flush; - engine->get_seqno = ring_get_seqno; - engine->set_seqno = ring_set_seqno; if (INTEL_GEN(dev_priv) >= 8) { engine->irq_enable_mask =