From patchwork Fri Aug 5 18:11:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paauwe, Bob J" X-Patchwork-Id: 9265665 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2C60F60760 for ; Fri, 5 Aug 2016 18:10:04 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1EB1728450 for ; Fri, 5 Aug 2016 18:10:04 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0FA7628458; Fri, 5 Aug 2016 18:10:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 91E8728450 for ; Fri, 5 Aug 2016 18:10:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 691716E10B; Fri, 5 Aug 2016 18:10:02 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 786B66E10B for ; Fri, 5 Aug 2016 18:10:01 +0000 (UTC) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP; 05 Aug 2016 11:10:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,474,1464678000"; d="scan'208";a="860455439" Received: from bpaauwe-desk.fm.intel.com ([10.1.134.207]) by orsmga003.jf.intel.com with ESMTP; 05 Aug 2016 11:10:01 -0700 From: Bob Paauwe To: intel-gfx Date: Fri, 5 Aug 2016 11:11:06 -0700 Message-Id: <1470420666-2910-1-git-send-email-bob.j.paauwe@intel.com> X-Mailer: git-send-email 2.7.4 Subject: [Intel-gfx] [PATCH] drm/i915/bxt: Bring MIPI out of reset (v2) X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP and power up the DSI regulator when initializing a MIPI display. v2: rebase on current drm-intel-nightly Signed-off-by: Bob Paauwe --- drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++ drivers/gpu/drm/i915/intel_dsi.c | 15 +++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f38a5e2..2caa22c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1275,11 +1275,19 @@ enum skl_disp_power_wells { #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) #define DPIO_UPAR_SHIFT 30 +/* BXT DSI Regulator registers */ +#define BXT_DSI_CFG _MMIO(0x160020) +#define STRAP_SELECT (1 << 0) + +#define BXT_DSI_TXCNTRL _MMIO(0x160054) +#define HS_IO_CONTROL_SELECT 0x0 + /* BXT PHY registers */ #define _BXT_PHY(phy, a, b) _MMIO_PIPE((phy), (a), (b)) #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) #define GT_DISPLAY_POWER_ON(phy) (1 << (phy)) +#define MIPIO_RST_CTRL (1 << 2) #define _BXT_PHY_CTL_DDI_A 0x64C00 #define _BXT_PHY_CTL_DDI_B 0x64C10 diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index de8e9fb..4100ea2 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -569,6 +569,21 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder) I915_WRITE(DSPCLK_GATE_D, val); } + if (IS_BROXTON(dev)) { + u32 val; + /* + * Bring the MIPI IO out of reset and power up + * the DSI regulator. + */ + val = I915_READ(BXT_P_CR_GT_DISP_PWRON); + val |= MIPIO_RST_CTRL; + I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); + + I915_WRITE(BXT_DSI_CFG, STRAP_SELECT); + I915_WRITE(BXT_DSI_TXCNTRL, HS_IO_CONTROL_SELECT); + } + + /* put device in ready state */ intel_dsi_device_ready(encoder);