[3/3] drm/i915/psr: adds psr2 status to debugfs
diff mbox

Message ID 1470901072-17525-4-git-send-email-vathsala.nagaraju@intel.com
State New
Headers show

Commit Message

vathsala nagaraju Aug. 11, 2016, 7:37 a.m. UTC
Reads from EDP_PSR2_CTL for psr2 and reports
live state of psr2

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: vathsala nagaraju <vathsala.nagaraju@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 36 ++++++++++++++++++++++++++++++++----
 drivers/gpu/drm/i915/i915_reg.h     |  2 ++
 2 files changed, 34 insertions(+), 4 deletions(-)

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 83f40e8..cfe238c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2673,9 +2673,12 @@  static int i915_edp_psr_status(struct seq_file *m, void *data)
 	seq_printf(m, "Re-enable work scheduled: %s\n",
 		   yesno(work_busy(&dev_priv->psr.work.work)));
 
-	if (HAS_DDI(dev))
-		enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
-	else {
+	if (HAS_DDI(dev)) {
+		if (dev_priv->psr.psr2_support)
+			enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE;
+		else
+			enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
+	} else {
 		for_each_pipe(dev_priv, pipe) {
 			stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
 				VLV_EDP_PSR_CURR_STATE_MASK;
@@ -2684,7 +2687,6 @@  static int i915_edp_psr_status(struct seq_file *m, void *data)
 				enabled = true;
 		}
 	}
-
 	seq_printf(m, "Main link in standby mode: %s\n",
 		   yesno(dev_priv->psr.link_standby));
 
@@ -2708,6 +2710,32 @@  static int i915_edp_psr_status(struct seq_file *m, void *data)
 
 		seq_printf(m, "Performance_Counter: %u\n", psrperf);
 	}
+
+	if (dev_priv->psr.psr2_support) {
+	static const char * const live_status[] = {
+				"idle",
+				"CAPTURE",
+				"CAPTURE_Fs",
+				"SLEEP",
+				"BUFON_FW",
+				"ML_UP",
+				"SU_STANDBY",
+				"FAST_SLEEP",
+				"DEEP_SLEEP",
+				"BUF_ON",
+				"TG_ON" };
+	u8 pos = (I915_READ(EDP_PSR2_STATUS_CTL) &
+		 EDP_PSR2_STATUS_STATE_MASK) >>
+		 EDP_PSR2_STATUS_STATE_SHIFT;
+
+		seq_printf(m, "PSR2_STATUS_EDP: %x\n",
+			  I915_READ(EDP_PSR2_STATUS_CTL));
+
+		if (pos <= EDP_PSR2_STATUS_TG_ON)
+			seq_printf(m, "PSR2 live state %s\n",
+				live_status[pos]);
+	}
+
 	mutex_unlock(&dev_priv->psr.lock);
 
 	intel_runtime_pm_put(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 49682f5..969d754 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3326,6 +3326,8 @@  enum {
 #define EDP_PSR2_STATUS_CTL		_MMIO(0x6f940)
 #define EDP_PSR2_STATUS_STATE_MASK	(0xf<<28)
 #define EDP_PSR2_STATUS_STATE_IDLE	0
+#define EDP_PSR2_STATUS_STATE_SHIFT	28
+#define EDP_PSR2_STATUS_TG_ON		0xa
 
 /* VGA port control */
 #define ADPA			_MMIO(0x61100)