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[v4,13/25] drm/i915/slpc: Send shutdown event

Message ID 1473236583-11533-14-git-send-email-sagar.a.kamble@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

sagar.a.kamble@intel.com Sept. 7, 2016, 8:22 a.m. UTC 
From: Tom O'Rourke <Tom.O'Rourke@intel.com>

Send SLPC shutdown event during disable, suspend, and reset
operations. Sending shutdown event while already shutdown
is OK.

v1: Return void instead of ignored error code (Paulo)
    Removed WARN_ON for checking msb of gtt address of
    shared gem obj. (ChrisW)
    Added SLPC state update during disable, suspend and reset.
    Changed semantics of reset. It is supposed to just disable. (Sagar)

Reviewed-by: David Weinehall <david.weinehall@linux.intel.com>
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c   |  6 ++++--
 drivers/gpu/drm/i915/intel_slpc.c | 17 +++++++++++++++++
 2 files changed, 21 insertions(+), 2 deletions(-)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2211f7b..70e08d9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6691,7 +6691,7 @@  void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 {
 	if (intel_slpc_enabled()) {
-		/* TODO: Set SLPC enabled forcefully */
+		dev_priv->guc.slpc.enabled = true;
 		intel_disable_gt_powersave(dev_priv);
 	} else {
 		dev_priv->rps.enabled = true; /* force disabling */
@@ -6704,8 +6704,10 @@  void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
 {
 	if (intel_slpc_enabled()) {
-		if (!intel_slpc_active(dev_priv))
+		if (!intel_slpc_active(dev_priv)) {
+			dev_priv->guc.slpc.enabled = false;
 			return;
+		}
 	} else if (!READ_ONCE(dev_priv->rps.enabled))
 		return;
 
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index eb3358a..f9d32c1 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -52,6 +52,19 @@  static void host2guc_slpc_reset(struct drm_i915_private *dev_priv)
 	host2guc_slpc(dev_priv, data, 4);
 }
 
+static void host2guc_slpc_shutdown(struct drm_i915_private *dev_priv)
+{
+	u32 data[4];
+	u32 shared_data_gtt_offset = i915_ggtt_offset(dev_priv->guc.slpc.vma);
+
+	data[0] = HOST2GUC_ACTION_SLPC_REQUEST;
+	data[1] = SLPC_EVENT(SLPC_EVENT_SHUTDOWN, 2);
+	data[2] = shared_data_gtt_offset;
+	data[3] = 0;
+
+	host2guc_slpc(dev_priv, data, 4);
+}
+
 static unsigned int slpc_get_platform_sku(struct drm_i915_private *dev_priv)
 {
 	enum slpc_platform_sku platform_sku;
@@ -149,10 +162,14 @@  void intel_slpc_cleanup(struct drm_i915_private *dev_priv)
 
 void intel_slpc_suspend(struct drm_i915_private *dev_priv)
 {
+	host2guc_slpc_shutdown(dev_priv);
+	dev_priv->guc.slpc.enabled = false;
 }
 
 void intel_slpc_disable(struct drm_i915_private *dev_priv)
 {
+	host2guc_slpc_shutdown(dev_priv);
+	dev_priv->guc.slpc.enabled = false;
 }
 
 void intel_slpc_enable(struct drm_i915_private *dev_priv)