drm/i915: Add ddb size field to device info structure
diff mbox

Message ID 1473841464-2131-1-git-send-email-m.deepak@intel.com
State New
Headers show

Commit Message

Deepak M Sept. 14, 2016, 8:24 a.m. UTC
Adding the ddb size into the devide info will avoid
platform checks while computing wm.

v2: Added comment and WARN_ON if ddb size is zero.(Jani)

Suggested-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Signed-off-by: Deepak M <m.deepak@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/i915_pci.c |  5 +++++
 drivers/gpu/drm/i915/intel_pm.c | 15 +++------------
 3 files changed, 9 insertions(+), 12 deletions(-)

Comments

Jani Nikula Sept. 15, 2016, 8:31 a.m. UTC | #1
On Wed, 14 Sep 2016, Deepak M <m.deepak@intel.com> wrote:
> Adding the ddb size into the devide info will avoid
> platform checks while computing wm.
>
> v2: Added comment and WARN_ON if ddb size is zero.(Jani)
>
> Suggested-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h |  1 +
>  drivers/gpu/drm/i915/i915_pci.c |  5 +++++
>  drivers/gpu/drm/i915/intel_pm.c | 15 +++------------
>  3 files changed, 9 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1e2dda8..6014c3a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -710,6 +710,7 @@ struct intel_device_info {
>  	u8 ring_mask; /* Rings supported by the HW */
>  	u8 num_rings;
>  	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
> +	u16 ddb_size; /* in blocks */
>  	/* Register offsets for the various display pipes and transcoders */
>  	int pipe_offsets[I915_MAX_TRANSCODERS];
>  	int trans_offsets[I915_MAX_TRANSCODERS];
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index d771870d..687c768 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -328,6 +328,7 @@ static const struct intel_device_info intel_skylake_info = {
>  	.gen = 9,
>  	.has_csr = 1,
>  	.has_guc = 1,
> +	.ddb_size = 896,
>  };
>  
>  static const struct intel_device_info intel_skylake_gt3_info = {
> @@ -336,6 +337,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
>  	.gen = 9,
>  	.has_csr = 1,
>  	.has_guc = 1,
> +	.ddb_size = 896,
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
>  };
>  
> @@ -358,6 +360,7 @@ static const struct intel_device_info intel_broxton_info = {
>  	.has_hw_contexts = 1,
>  	.has_logical_ring_contexts = 1,
>  	.has_guc = 1,
> +	.ddb_size = 512,
>  	GEN_DEFAULT_PIPEOFFSETS,
>  	IVB_CURSOR_OFFSETS,
>  	BDW_COLORS,
> @@ -369,6 +372,7 @@ static const struct intel_device_info intel_kabylake_info = {
>  	.gen = 9,
>  	.has_csr = 1,
>  	.has_guc = 1,
> +	.ddb_size = 896,
>  };
>  
>  static const struct intel_device_info intel_kabylake_gt3_info = {
> @@ -377,6 +381,7 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
>  	.gen = 9,
>  	.has_csr = 1,
>  	.has_guc = 1,
> +	.ddb_size = 896,
>  	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
>  };
>  
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6af438f..9c5861e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2853,13 +2853,6 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
>  	return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
>  }
>  
> -/*
> - * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
> - * different active planes.
> - */
> -
> -#define SKL_DDB_SIZE		896	/* in blocks */
> -#define BXT_DDB_SIZE		512
>  #define SKL_SAGV_BLOCK_TIME	30 /* µs */
>  
>  /*
> @@ -3057,13 +3050,11 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
>  	else
>  		*num_active = hweight32(dev_priv->active_crtcs);
>  
> -	if (IS_BROXTON(dev))
> -		ddb_size = BXT_DDB_SIZE;
> -	else
> -		ddb_size = SKL_DDB_SIZE;
> -
> +	ddb_size = INTEL_INFO(dev_priv)->ddb_size;
>  	ddb_size -= 4; /* 4 blocks for bypass path allocation */
>  
> +	WARN_ON(ddb_size == 0);

Please be careful. You have to stick the WARN_ON *before* you decrement
by 4.

BR,
Jani.


> +
>  	/*
>  	 * If the state doesn't change the active CRTC's, then there's
>  	 * no need to recalculate; the existing pipe allocation limits

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1e2dda8..6014c3a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -710,6 +710,7 @@  struct intel_device_info {
 	u8 ring_mask; /* Rings supported by the HW */
 	u8 num_rings;
 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
+	u16 ddb_size; /* in blocks */
 	/* Register offsets for the various display pipes and transcoders */
 	int pipe_offsets[I915_MAX_TRANSCODERS];
 	int trans_offsets[I915_MAX_TRANSCODERS];
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index d771870d..687c768 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -328,6 +328,7 @@  static const struct intel_device_info intel_skylake_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 };
 
 static const struct intel_device_info intel_skylake_gt3_info = {
@@ -336,6 +337,7 @@  static const struct intel_device_info intel_skylake_gt3_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
@@ -358,6 +360,7 @@  static const struct intel_device_info intel_broxton_info = {
 	.has_hw_contexts = 1,
 	.has_logical_ring_contexts = 1,
 	.has_guc = 1,
+	.ddb_size = 512,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 	BDW_COLORS,
@@ -369,6 +372,7 @@  static const struct intel_device_info intel_kabylake_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 };
 
 static const struct intel_device_info intel_kabylake_gt3_info = {
@@ -377,6 +381,7 @@  static const struct intel_device_info intel_kabylake_gt3_info = {
 	.gen = 9,
 	.has_csr = 1,
 	.has_guc = 1,
+	.ddb_size = 896,
 	.ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 };
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6af438f..9c5861e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2853,13 +2853,6 @@  bool ilk_disable_lp_wm(struct drm_device *dev)
 	return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
 }
 
-/*
- * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
- * different active planes.
- */
-
-#define SKL_DDB_SIZE		896	/* in blocks */
-#define BXT_DDB_SIZE		512
 #define SKL_SAGV_BLOCK_TIME	30 /* µs */
 
 /*
@@ -3057,13 +3050,11 @@  skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
 	else
 		*num_active = hweight32(dev_priv->active_crtcs);
 
-	if (IS_BROXTON(dev))
-		ddb_size = BXT_DDB_SIZE;
-	else
-		ddb_size = SKL_DDB_SIZE;
-
+	ddb_size = INTEL_INFO(dev_priv)->ddb_size;
 	ddb_size -= 4; /* 4 blocks for bypass path allocation */
 
+	WARN_ON(ddb_size == 0);
+
 	/*
 	 * If the state doesn't change the active CRTC's, then there's
 	 * no need to recalculate; the existing pipe allocation limits