[5/5] drm/i915: enable PIPE_CONTROL on all 965 class chips

Commit Message

Jesse Barnes April 21, 2010, 6:39 p.m. UTC

None

Patch

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 71ae2f1..4b9a12f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1156,7 +1156,7 @@  extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 
 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
-#define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev))
+#define HAS_PIPE_CONTROL(dev) (IS_I965G(dev))
 
 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
 
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 06a743f..f1e85b6 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -51,9 +51,6 @@ 
 	 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |	\
 	 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 
-/** Interrupts that we mask and unmask at runtime. */
-#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
-
 #define I915_PIPE_VBLANK_STATUS	(PIPE_START_VBLANK_INTERRUPT_STATUS |\
 				 PIPE_VBLANK_INTERRUPT_STATUS)
 
@@ -922,8 +919,13 @@  irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 					READ_BREADCRUMB(dev_priv);
 		}
 
-		if (iir & I915_USER_INTERRUPT) {
+		if (iir &
+		    (I915_USER_INTERRUPT | I915_PIPE_CONTROL_NOTIFY_INTERRUPT)) {
 			u32 seqno = i915_get_gem_seqno(dev);
+
+			if (IS_I965G(dev) && (iir & I915_USER_INTERRUPT))
+				DRM_DEBUG_DRIVER("unexpected user interrupt\n");
+
 			dev_priv->mm.irq_gem_seqno = seqno;
 			trace_i915_gem_request_complete(dev, seqno);
 			DRM_WAKEUP(&dev_priv->irq_queue);
@@ -1005,13 +1007,19 @@  void i915_user_irq_get(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	unsigned long irqflags;
+	u32 irq;
+
+	if (IS_I965G(dev))
+		irq = I915_PIPE_CONTROL_NOTIFY_INTERRUPT;
+	else
+		irq = I915_USER_INTERRUPT;
 
 	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 	if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
 		if (HAS_PCH_SPLIT(dev))
 			ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
 		else
-			i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
+			i915_enable_irq(dev_priv, irq);
 	}
 	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 }
@@ -1020,6 +1028,12 @@  void i915_user_irq_put(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 	unsigned long irqflags;
+	u32 irq;
+
+	if (IS_I965G(dev))
+		irq = I915_PIPE_CONTROL_NOTIFY_INTERRUPT;
+	else
+		irq = I915_USER_INTERRUPT;
 
 	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 	BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
@@ -1027,7 +1041,7 @@  void i915_user_irq_put(struct drm_device *dev)
 		if (HAS_PCH_SPLIT(dev))
 			ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
 		else
-			i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
+			i915_disable_irq(dev_priv, irq);
 	}
 	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 }
@@ -1383,7 +1397,7 @@  void i915_driver_irq_preinstall(struct drm_device * dev)
 int i915_driver_irq_postinstall(struct drm_device *dev)
 {
 	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-	u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
+	u32 enable_mask = I915_INTERRUPT_ENABLE_FIX;
 	u32 error_mask;
 
 	DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
@@ -1393,6 +1407,11 @@  int i915_driver_irq_postinstall(struct drm_device *dev)
 	if (HAS_PCH_SPLIT(dev))
 		return ironlake_irq_postinstall(dev);
 
+	if (IS_I965G(dev))
+		enable_mask |= I915_PIPE_CONTROL_NOTIFY_INTERRUPT;
+	else
+		enable_mask |= I915_USER_INTERRUPT;
+
 	/* Unmask the interrupts that we always want on. */
 	dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;