From patchwork Wed Nov 2 17:50:40 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 9409681 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E4EBD601C2 for ; Wed, 2 Nov 2016 17:50:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DE3692A4DF for ; Wed, 2 Nov 2016 17:50:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D33DD2A4E1; Wed, 2 Nov 2016 17:50:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.6 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,RCVD_IN_SORBS_SPAM,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5696A2A4DF for ; Wed, 2 Nov 2016 17:50:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9E7276E570; Wed, 2 Nov 2016 17:50:57 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) by gabe.freedesktop.org (Postfix) with ESMTPS id EF3B86E570 for ; Wed, 2 Nov 2016 17:50:56 +0000 (UTC) Received: by mail-wm0-x241.google.com with SMTP id c17so4169588wmc.3 for ; Wed, 02 Nov 2016 10:50:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=GKXTY2HGEH8CfWhsbuzkXqezVcrTyuH4Dv0Z1wm/Vnk=; b=zG+RBF6a0qVbTCT2qOmfpb+wQ0F8R9aO4vGofjmo9u7RHdrFK6nRVo9GgwDJNw3klv 98klCfy6U2eQUiNCvfo1g6ih/HwAqO9cMuA59/HlM+1FMdNAUI6o5Z2X4ymBjJm8yIp9 /kzJuT8WCRO08SJOimrOEAf+F0Q7rFpGocQWyOqBzeDEftsQKLY5NQeWKAJqlHSn0lwx rgKt+cmNyo0vSsnWKu659QVh48SUJQz1ZCchmOdW4ti/3iLPMII0zYMmoSKK5uCKkQFm G3jJCOC2idWLXmDm/mKs/q8ma3HSsB+aySP59sGPnEzN3EIIVcqXJ9zgKAddbjb8ydDa +HJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=GKXTY2HGEH8CfWhsbuzkXqezVcrTyuH4Dv0Z1wm/Vnk=; b=EOClmVTlUOdZ71hywPOwfO9pErBGh+nXiJOaipHtEkKtJbjJqpQaE5+xpPzxbe6XpA BrV+7cC4ozP//++QPj2ee3M6c56Ck8KC76ERlsDPHcvg2SGKCzKl9zvh8iFogpXcTywC L+37X5HIJQzA2zyN3kpdmYb4pwwizU8Ivb7JuIMpFGHiAxyI3a+GYtyonjRMJy15RoyJ 7+S8K3T+KH8jm2K3IgnSFHYc/O9UXWRjzBD6t8mA8/MlcnRCnThyJ8Oi/xdBy0KZ46LE dqL3U3p95qf/gKhy3ahyA3o747Euq5Y6EQ29Zp8vYTZ7r3QZggm8lXaE+gXueynfw6Y7 IU/A== X-Gm-Message-State: ABUngvc/5YTGZyA9sLFM6GxkX3dALdVHbfS6zC2VwRiFb6Lr0IT29EiuIAbDh2wQHUUHpA== X-Received: by 10.194.176.40 with SMTP id cf8mr3939995wjc.68.1478109055486; Wed, 02 Nov 2016 10:50:55 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id e2sm4065605wjw.14.2016.11.02.10.50.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Nov 2016 10:50:54 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Wed, 2 Nov 2016 17:50:40 +0000 Message-Id: <20161102175051.29163-2-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20161102175051.29163-1-chris@chris-wilson.co.uk> References: <20161102175051.29163-1-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 01/12] drm/i915: Split request submit/execute phase into two X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP In order to support deferred scheduling, we need to differentiate between when the request is ready to run (i.e. the submit fence is signaled) and when the request is actually run (a new execute fence). This is typically split between the request itself wanting to wait upon others (for which we use the submit fence) and the CPU wanting to wait upon the request, for which we use the execute fence to be sure the hardware is ready to signal completion. Signed-off-by: Chris Wilson Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_gem_request.c | 33 ++++++++++++++++++++++++--------- drivers/gpu/drm/i915/i915_gem_request.h | 2 ++ 2 files changed, 26 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index 79b0046d9a57..1ae5a2f8953f 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -351,11 +351,19 @@ submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) list_move_tail(&request->link, &timeline->requests); spin_unlock(&request->timeline->lock); + i915_sw_fence_commit(&request->execute); + spin_unlock_irqrestore(&timeline->lock, flags); return NOTIFY_DONE; } +static int __i915_sw_fence_call +execute_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) +{ + return NOTIFY_DONE; +} + /** * i915_gem_request_alloc - allocate a request structure * @@ -441,6 +449,12 @@ i915_gem_request_alloc(struct intel_engine_cs *engine, __timeline_get_seqno(req->timeline->common)); i915_sw_fence_init(&req->submit, submit_notify); + i915_sw_fence_init(&req->execute, execute_notify); + /* Ensure that the execute fence completes after the submit fence - + * as we complete the execute fence from within the submit fence + * callback, its completion would otherwise be visible first. + */ + i915_sw_fence_await_sw_fence(&req->execute, &req->submit, &req->execq); INIT_LIST_HEAD(&req->active_list); req->i915 = dev_priv; @@ -817,9 +831,9 @@ bool __i915_spin_request(const struct drm_i915_gem_request *req, } static long -__i915_request_wait_for_submit(struct drm_i915_gem_request *request, - unsigned int flags, - long timeout) +__i915_request_wait_for_execute(struct drm_i915_gem_request *request, + unsigned int flags, + long timeout) { const int state = flags & I915_WAIT_INTERRUPTIBLE ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; @@ -831,9 +845,9 @@ __i915_request_wait_for_submit(struct drm_i915_gem_request *request, add_wait_queue(q, &reset); do { - prepare_to_wait(&request->submit.wait, &wait, state); + prepare_to_wait(&request->execute.wait, &wait, state); - if (i915_sw_fence_done(&request->submit)) + if (i915_sw_fence_done(&request->execute)) break; if (flags & I915_WAIT_LOCKED && @@ -851,7 +865,7 @@ __i915_request_wait_for_submit(struct drm_i915_gem_request *request, timeout = io_schedule_timeout(timeout); } while (timeout); - finish_wait(&request->submit.wait, &wait); + finish_wait(&request->execute.wait, &wait); if (flags & I915_WAIT_LOCKED) remove_wait_queue(q, &reset); @@ -903,13 +917,14 @@ long i915_wait_request(struct drm_i915_gem_request *req, trace_i915_gem_request_wait_begin(req); - if (!i915_sw_fence_done(&req->submit)) { - timeout = __i915_request_wait_for_submit(req, flags, timeout); + if (!i915_sw_fence_done(&req->execute)) { + timeout = __i915_request_wait_for_execute(req, flags, timeout); if (timeout < 0) goto complete; - GEM_BUG_ON(!i915_sw_fence_done(&req->submit)); + GEM_BUG_ON(!i915_sw_fence_done(&req->execute)); } + GEM_BUG_ON(!i915_sw_fence_done(&req->submit)); GEM_BUG_ON(!req->global_seqno); /* Optimistic short spin before touching IRQs */ diff --git a/drivers/gpu/drm/i915/i915_gem_request.h b/drivers/gpu/drm/i915/i915_gem_request.h index 75f8360b3421..ed13f37fea0f 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.h +++ b/drivers/gpu/drm/i915/i915_gem_request.h @@ -85,7 +85,9 @@ struct drm_i915_gem_request { struct intel_signal_node signaling; struct i915_sw_fence submit; + struct i915_sw_fence execute; wait_queue_t submitq; + wait_queue_t execq; u32 global_seqno;