[v3,08/11] drm/tilcdc: Call reset() before loading the palette

Commit Message

Jyri Sarha Nov. 22, 2016, 4:54 p.m. UTC

The palette loading does not work reliably without LCDC SW reset
before it. The AM335x TRM suggests this [1] after L3 clock domain has
been shut down. We have no knowledge of such events so we do it
always. The software reset will clear all the frame information in the
FIFO. Upon a restart, the L3 DMA will fetch from the fb0_base address
[2].

[1] Section 13.3.8 in AM335x TRM (http://www.ti.com/lit/pdf/sprz360)
[2] Section 13.4.6 in AM335x TRM

Signed-off-by: Jyri Sarha <[e-mail]>
---
 drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 4 ++++
 1 file changed, 4 insertions(+)

Patch

diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index fbb41b1..963e0a0 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -113,6 +113,7 @@  static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
 	tilcdc_crtc->curr_fb = fb;
 }
 
+static void reset(struct drm_crtc *crtc);
 /*
  * The driver currently only supports only true color formats. For
  * true color the palette block is bypassed, but a 32 byte palette
@@ -131,6 +132,9 @@  static void tilcdc_crtc_load_palette(struct drm_crtc *crtc)
 	dma_fb_ceiling = tilcdc_read(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG);
 	raster_ctl = tilcdc_read(dev, LCDC_RASTER_CTRL_REG);
 
+	/* SW reset before turning DMA on (see section 13.3.8 in AM335x TRM)*/
+	reset(crtc);
+
 	/* Tell the LCDC where the palette is located. */
 	tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG,
 		     tilcdc_crtc->palette_dma_handle);