[2/2] clk: bcm: Allow rate change propagation to PLLH_AUX on VEC clock
diff mbox

Message ID 1480626020-20031-3-git-send-email-boris.brezillon@free-electrons.com
State Accepted, archived
Delegated to: Stephen Boyd
Headers show

Commit Message

Boris BREZILLON Dec. 1, 2016, 9 p.m. UTC
The VEC clock requires needs to be set at exactly 108MHz. Allow rate
change propagation on PLLH_AUX to match this requirement wihtout
impacting other IPs (PLLH is currently only used by the HDMI encoder,
which cannot be enabled when the VEC encoder is enabled).

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
---
 drivers/clk/bcm/clk-bcm2835.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

Comments

Stephen Boyd Dec. 8, 2016, 11:06 p.m. UTC | #1
On 12/01, Boris Brezillon wrote:
> The VEC clock requires needs to be set at exactly 108MHz. Allow rate
> change propagation on PLLH_AUX to match this requirement wihtout
> impacting other IPs (PLLH is currently only used by the HDMI encoder,
> which cannot be enabled when the VEC encoder is enabled).
> 
> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
> ---

Applied to clk-next

Patch
diff mbox

diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index df96fe6dadab..eaf82f49dede 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -1861,7 +1861,12 @@  static const struct bcm2835_clk_desc clk_desc_array[] = {
 		.ctl_reg = CM_VECCTL,
 		.div_reg = CM_VECDIV,
 		.int_bits = 4,
-		.frac_bits = 0),
+		.frac_bits = 0,
+		/*
+		 * Allow rate change propagation only on PLLH_AUX which is
+		 * assigned index 7 in the parent array.
+		 */
+		.set_rate_parent = BIT(7)),
 
 	/* dsi clocks */
 	[BCM2835_CLOCK_DSI0E]	= REGISTER_PER_CLK(