[2/2] ASoC: nau8825: provide clock divide for codec mater mode
diff mbox

Message ID 1482223627-23547-2-git-send-email-KCHSU0@nuvoton.com
State New
Headers show

Commit Message

AS50 KCHsu0 Dec. 20, 2016, 8:47 a.m. UTC
Provide the LRC and BCLK divide. The clock divide needs configuration
properly when codec in master mode.

Signed-off-by: John Hsu <KCHSU0@nuvoton.com>
---
 sound/soc/codecs/nau8825.c | 26 ++++++++++++++++++++++++++
 sound/soc/codecs/nau8825.h |  6 ++++++
 2 files changed, 32 insertions(+)

Comments

Mark Brown Dec. 31, 2016, 6:57 p.m. UTC | #1
On Tue, Dec 20, 2016 at 04:47:07PM +0800, John Hsu wrote:
> Provide the LRC and BCLK divide. The clock divide needs configuration
> properly when codec in master mode.

Why is the driver not able to configure these automatically, most
devices manage to do that OK?  Typically systems are fine with the
obvious divisions down from the root clock, the driver should at least
offer that as a default rather than requiring all machine drivers to
duplicate the divisor selection code.
AS50 KCHsu0 Jan. 3, 2017, 3:04 a.m. UTC | #2
On 1/1/2017 2:57 AM, Mark Brown wrote:
> On Tue, Dec 20, 2016 at 04:47:07PM +0800, John Hsu wrote:
>
>> Provide the LRC and BCLK divide. The clock divide needs configuration
>> properly when codec in master mode.
>>
>
> Why is the driver not able to configure these automatically, most
> devices manage to do that OK?  Typically systems are fine with the
> obvious divisions down from the root clock, the driver should at least
> offer that as a default rather than requiring all machine drivers to
> duplicate the divisor selection code.
>

The system clock of codec is always 256FS. Therefore, the driver can
make it automatically. If the codec is as master, the driver needs to
divide the system clock to output the BCLK and FS. But there are too
many combinations between BCLK and FS. The BCLK maybe is 32FS, 64FS,
128FS, etc. The driver needs machine information to do the division.
Thus, I think the best way is to make decision by machine driver.



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Mark Brown Jan. 9, 2017, 11:42 a.m. UTC | #3
On Tue, Jan 03, 2017 at 11:04:50AM +0800, John Hsu wrote:
> On 1/1/2017 2:57 AM, Mark Brown wrote:

> > Why is the driver not able to configure these automatically, most
> > devices manage to do that OK?  Typically systems are fine with the
> > obvious divisions down from the root clock, the driver should at least
> > offer that as a default rather than requiring all machine drivers to
> > duplicate the divisor selection code.

> The system clock of codec is always 256FS. Therefore, the driver can
> make it automatically. If the codec is as master, the driver needs to
> divide the system clock to output the BCLK and FS. But there are too
> many combinations between BCLK and FS. The BCLK maybe is 32FS, 64FS,
> 128FS, etc. The driver needs machine information to do the division.
> Thus, I think the best way is to make decision by machine driver.

This all sounds totally standard - other drivers manage to provide a
default easily enough here.  You can determine a default BCLK by looking
at the number of channels and number of bits per sample to work out how
many BCLKs are going to be needed to clock that data out.
AS50 KCHsu0 Jan. 23, 2017, 8:39 a.m. UTC | #4
Hi,

On 1/9/2017 7:42 PM, Mark Brown wrote:
> On Tue, Jan 03, 2017 at 11:04:50AM +0800, John Hsu wrote:
>
>> On 1/1/2017 2:57 AM, Mark Brown wrote:
>>
>
>
>>> Why is the driver not able to configure these automatically, most
>>> devices manage to do that OK?  Typically systems are fine with the
>>> obvious divisions down from the root clock, the driver should at least
>>> offer that as a default rather than requiring all machine drivers to
>>> duplicate the divisor selection code.
>>>
>
>
>> The system clock of codec is always 256FS. Therefore, the driver can
>> make it automatically. If the codec is as master, the driver needs to
>> divide the system clock to output the BCLK and FS. But there are too
>> many combinations between BCLK and FS. The BCLK maybe is 32FS, 64FS,
>> 128FS, etc. The driver needs machine information to do the division.
>> Thus, I think the best way is to make decision by machine driver.
>>
>
> This all sounds totally standard - other drivers manage to provide a
> default easily enough here.  You can determine a default BCLK by looking
> at the number of channels and number of bits per sample to work out how
> many BCLKs are going to be needed to clock that data out.
>

I see. The driver should be able to handle it. I'll make another
patch to support the clock divide automatically.



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Patch
diff mbox

diff --git a/sound/soc/codecs/nau8825.c b/sound/soc/codecs/nau8825.c
index 9c98d35..3c7a801 100644
--- a/sound/soc/codecs/nau8825.c
+++ b/sound/soc/codecs/nau8825.c
@@ -1421,9 +1421,35 @@  static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 	return 0;
 }
 
+static int nau8825_set_clkdiv(struct snd_soc_dai *codec_dai,
+	int div_id, int div)
+{
+	struct snd_soc_codec *codec = codec_dai->codec;
+	struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
+
+	switch (div_id) {
+	case NAU8825_BCLKDIV:
+		regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
+			NAU8825_I2S_BLK_DIV_MASK, div);
+		break;
+
+	case NAU8825_FSDIV:
+		regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
+			NAU8825_I2S_LRC_DIV_MASK,
+			div << NAU8825_I2S_LRC_DIV_SFT);
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static const struct snd_soc_dai_ops nau8825_dai_ops = {
 	.hw_params	= nau8825_hw_params,
 	.set_fmt	= nau8825_set_dai_fmt,
+	.set_clkdiv	= nau8825_set_clkdiv,
 };
 
 #define NAU8825_RATES	SNDRV_PCM_RATE_8000_192000
diff --git a/sound/soc/codecs/nau8825.h b/sound/soc/codecs/nau8825.h
index 4b390c4..58b8554 100644
--- a/sound/soc/codecs/nau8825.h
+++ b/sound/soc/codecs/nau8825.h
@@ -425,6 +425,12 @@ 
 #define NAU8825_CHANRGE_PUMP_EN	(1 << 5)
 
 
+/* Programmable divide */
+enum {
+	NAU8825_BCLKDIV,
+	NAU8825_FSDIV,
+};
+
 /* System Clock Source */
 enum {
 	NAU8825_CLK_DIS = 0,