From patchwork Fri Dec 30 01:32:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniele Ceraolo Spurio X-Patchwork-Id: 9491691 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1EBDF62ABA for ; Fri, 30 Dec 2016 01:33:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0AFC91FF60 for ; Fri, 30 Dec 2016 01:33:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F0117200F5; Fri, 30 Dec 2016 01:33:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6DBD21FF60 for ; Fri, 30 Dec 2016 01:33:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 44B816E1B0; Fri, 30 Dec 2016 01:32:59 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id AB1F26E1B0 for ; Fri, 30 Dec 2016 01:32:57 +0000 (UTC) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 29 Dec 2016 17:32:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.33,428,1477983600"; d="scan'208"; a="1105855434" Received: from relo-linux-1.fm.intel.com ([10.1.27.60]) by fmsmga002.fm.intel.com with ESMTP; 29 Dec 2016 17:32:56 -0800 From: daniele.ceraolospurio@intel.com To: intel-gfx@lists.freedesktop.org Date: Thu, 29 Dec 2016 17:32:47 -0800 Message-Id: <1483061567-7258-1-git-send-email-daniele.ceraolospurio@intel.com> X-Mailer: git-send-email 1.9.1 Subject: [Intel-gfx] [PATCH] drm/i915/guc: fix mmio whitelist mmio_start offset and add reminder X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Daniele Ceraolo Spurio The mmio_start offset for the whitelist is the first FORCE_TO_NONPRIV register the GuC can use to restore the provided whitelist when an engine reset via GuC (which we still don't support) is triggered. We're currently adding the mmio_base of the engine to the absolute address of the RCS version of the register, which results in the wrong offset. Fix it by using the definition we already have instead of re-defining it in the GuC FW header. Also add a comment to avoid future issues with FORCE_TO_NONPRIV registers, which are also used by the workaround framework. Compile tested only as my SKL died early this week. Signed-off-by: Daniele Ceraolo Spurio Cc: Michal Wajdeczko Cc: Arkadiusz Hiler --- drivers/gpu/drm/i915/i915_guc_submission.c | 9 +++++++-- drivers/gpu/drm/i915/intel_guc_fwif.h | 1 - 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index 30e012b..7a1c6a0 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -1336,9 +1336,14 @@ static void guc_addon_create(struct intel_guc *guc) for_each_engine(engine, dev_priv, id) { reg_state->mmio_white_list[engine->guc_id].mmio_start = - engine->mmio_base + GUC_MMIO_WHITE_LIST_START; + i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(engine->mmio_base, 0)); - /* Nothing to be saved or restored for now. */ + /* + * Nothing to be saved or restored for now. + * XXX: when adding registers to the whitelist, make sure to not + * conflict with what the workaround framework is doing with + * the FORCE_TO_NONPRIV registers. + */ reg_state->mmio_white_list[engine->guc_id].count = 0; } diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h index 3202b32..2841d59 100644 --- a/drivers/gpu/drm/i915/intel_guc_fwif.h +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h @@ -371,7 +371,6 @@ struct guc_policies { #define GUC_REGSET_SAVE_CURRENT_VALUE 0x10 #define GUC_REGSET_MAX_REGISTERS 25 -#define GUC_MMIO_WHITE_LIST_START 0x24d0 #define GUC_MMIO_WHITE_LIST_MAX 12 #define GUC_S3_SAVE_SPACE_PAGES 10