drm/i915: check ppgtt validity when init reg state
diff mbox

Message ID 20170109091601.4915-1-zhenyuw@linux.intel.com
State New
Headers show

Commit Message

Zhenyu Wang Jan. 9, 2017, 9:16 a.m. UTC
Check if ppgtt is valid for context when init reg state. For gvt
context which has no i915 allocated ppgtt, failed to check that
would cause kernel null ptr reference error.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 28 +++++++++++++++-------------
 1 file changed, 15 insertions(+), 13 deletions(-)

Comments

Chris Wilson Jan. 9, 2017, 12:04 p.m. UTC | #1
On Mon, Jan 09, 2017 at 05:16:01PM +0800, Zhenyu Wang wrote:
> Check if ppgtt is valid for context when init reg state. For gvt
> context which has no i915 allocated ppgtt, failed to check that
> would cause kernel null ptr reference error.
> 
> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

Bah, we could remove the !48bit path here since we always set it prior
to submission (i.e. if (ppgtt && USE_FULL_48BIT_PPGTT()) {} )
That would look more symmetrical.
-Chris
Tvrtko Ursulin Jan. 12, 2017, 8:47 a.m. UTC | #2
On 09/01/2017 13:53, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: check ppgtt validity when init reg state (rev2)
> URL   : https://patchwork.freedesktop.org/series/17691/
> State : warning
>
> == Summary ==
>
> Series 17691v2 drm/i915: check ppgtt validity when init reg state
> https://patchwork.freedesktop.org/api/1.0/series/17691/revisions/2/mbox/
>
> Test drv_module_reload:
>         Subgroup basic-reload-final:
>                 pass       -> DMESG-WARN (fi-skl-6770hq)

FIFO underrun, https://bugs.freedesktop.org/show_bug.cgi?id=98041

> Test kms_force_connector_basic:
>         Subgroup force-connector-state:
>                 pass       -> SKIP       (fi-snb-2520m)
>
> fi-bdw-5557u     total:246  pass:232  dwarn:0   dfail:0   fail:0   skip:14
> fi-bsw-n3050     total:246  pass:207  dwarn:0   dfail:0   fail:0   skip:39
> fi-bxt-j4205     total:246  pass:224  dwarn:0   dfail:0   fail:0   skip:22
> fi-bxt-t5700     total:82   pass:69   dwarn:0   dfail:0   fail:0   skip:12
> fi-byt-j1900     total:246  pass:219  dwarn:0   dfail:0   fail:0   skip:27
> fi-byt-n2820     total:246  pass:215  dwarn:0   dfail:0   fail:0   skip:31
> fi-hsw-4770      total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19
> fi-hsw-4770r     total:246  pass:227  dwarn:0   dfail:0   fail:0   skip:19
> fi-ivb-3520m     total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21
> fi-ivb-3770      total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21
> fi-kbl-7500u     total:246  pass:225  dwarn:0   dfail:0   fail:0   skip:21
> fi-skl-6260u     total:246  pass:233  dwarn:0   dfail:0   fail:0   skip:13
> fi-skl-6700hq    total:246  pass:226  dwarn:0   dfail:0   fail:0   skip:20
> fi-skl-6700k     total:246  pass:222  dwarn:3   dfail:0   fail:0   skip:21
> fi-skl-6770hq    total:246  pass:232  dwarn:1   dfail:0   fail:0   skip:13
> fi-snb-2520m     total:246  pass:214  dwarn:0   dfail:0   fail:0   skip:32
> fi-snb-2600      total:246  pass:214  dwarn:0   dfail:0   fail:0   skip:32
>
> 60cfa8f499c9e441f1cf9d267dbf67dcde60f5f4 drm-tip: 2017y-01m-09d-11h-56m-04s UTC integration manifest
> fcd90dc drm/i915: check ppgtt validity when init reg state

Pushed to dinq, thanks for the patch and review.

Regards,

Tvrtko

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6db246ad2f13..8f10927f6c84 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -2103,19 +2103,21 @@  static void execlists_init_reg_state(u32 *reg_state,
 	ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
 		       0);
 
-	if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
-		/* 64b PPGTT (48bit canonical)
-		 * PDP0_DESCRIPTOR contains the base address to PML4 and
-		 * other PDP Descriptors are ignored.
-		 */
-		ASSIGN_CTX_PML4(ppgtt, reg_state);
-	} else {
-		/* 32b PPGTT
-		 * PDP*_DESCRIPTOR contains the base address of space supported.
-		 * With dynamic page allocation, PDPs may not be allocated at
-		 * this point. Point the unallocated PDPs to the scratch page
-		 */
-		execlists_update_context_pdps(ppgtt, reg_state);
+	if (ppgtt) {
+		if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
+			/* 64b PPGTT (48bit canonical)
+			 * PDP0_DESCRIPTOR contains the base address to PML4 and
+			 * other PDP Descriptors are ignored.
+			 */
+			ASSIGN_CTX_PML4(ppgtt, reg_state);
+		} else {
+			/* 32b PPGTT
+			 * PDP*_DESCRIPTOR contains the base address of space supported.
+			 * With dynamic page allocation, PDPs may not be allocated at
+			 * this point. Point the unallocated PDPs to the scratch page
+			 */
+			execlists_update_context_pdps(ppgtt, reg_state);
+		}
 	}
 
 	if (engine->id == RCS) {