| Message ID | 1484252284-29291-6-git-send-email-laurent@vivier.eu (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 12.01.2017 21:18, Laurent Vivier wrote: > Address Register indirect With postincrement: > > When using the stack pointer (A7) with byte size data, the register > is incremented by two. > > Address Register indirect With predecrement: > > When using the stack pointer (A7) with byte size data, the register > is decremented by two. I think this is only valid for the full 680x0 CPUs. According to http://www.nxp.com/assets/documents/data/en/reference-manuals/CFPRM.pdf the stack pointer behaves differently on ColdFire: "2.2.5 Address Register Indirect with Predecrement Mode [...] Note that the stack pointer (A7) is treated just like the other address registers." Thomas
Le 12/01/2017 à 22:14, Thomas Huth a écrit : > On 12.01.2017 21:18, Laurent Vivier wrote: >> Address Register indirect With postincrement: >> >> When using the stack pointer (A7) with byte size data, the register >> is incremented by two. >> >> Address Register indirect With predecrement: >> >> When using the stack pointer (A7) with byte size data, the register >> is decremented by two. > > I think this is only valid for the full 680x0 CPUs. According to > http://www.nxp.com/assets/documents/data/en/reference-manuals/CFPRM.pdf > the stack pointer behaves differently on ColdFire: > > "2.2.5 Address Register Indirect with Predecrement Mode [...] > Note that the stack pointer (A7) is treated just like the other address > registers." Yes, you're right. This is true only for 680x0: "MOTOROLA M68000 FAMILY Programmer’s Reference Manual" "2.2.5 Address Register Indirect with Predecrement Mode ... If the address register is thestack pointer and the operand size is byte, the address is decremented by two to keep the stack pointer aligned to a word boundary." Thank you, I will update this patch accordingly. Laurent
diff --git a/target/m68k/translate.c b/target/m68k/translate.c index cf5d8dd..c83d902 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -725,7 +725,10 @@ static TCGv gen_lea_mode(CPUM68KState *env, DisasContext *s, } reg = get_areg(s, reg0); tmp = tcg_temp_new(); - tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize)); + tcg_gen_subi_i32(tmp, reg, + reg0 == 7 && opsize == OS_BYTE + ? 2 + : opsize_bytes(opsize)); return tmp; case 5: /* Indirect displacement. */ reg = get_areg(s, reg0); @@ -801,7 +804,10 @@ static TCGv gen_ea_mode(CPUM68KState *env, DisasContext *s, int mode, int reg0, result = gen_ldst(s, opsize, reg, val, what); if (what == EA_STORE || !addrp) { TCGv tmp = tcg_temp_new(); - tcg_gen_addi_i32(tmp, reg, opsize_bytes(opsize)); + tcg_gen_addi_i32(tmp, reg, + reg0 == 7 && opsize == OS_BYTE + ? 2 + : opsize_bytes(opsize)); delay_set_areg(s, reg0, tmp, true); } return result;
Address Register indirect With postincrement: When using the stack pointer (A7) with byte size data, the register is incremented by two. Address Register indirect With predecrement: When using the stack pointer (A7) with byte size data, the register is decremented by two. Signed-off-by: Laurent Vivier <laurent@vivier.eu> --- target/m68k/translate.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)