diff mbox

[2/2] ASoC: mxs-saif: fix setting SAIF1 register

Message ID 20170113204428.16703-2-joerg.krause@embedded.rocks (mailing list archive)
State Accepted
Commit b25658ed7d24cd8b1f9a72148e80e216b6a0c17a
Headers show

Commit Message

Jörg Krause Jan. 13, 2017, 8:44 p.m. UTC 
If SAIF0 is used in master and SAIF1 in slave mode setting the SAIF1
register in mxs_saif_set_dai_fmt() does not have any effect on the
interface as the clk gate needs to be cleared before the register can be
written.

Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
---
 sound/soc/mxs/mxs-saif.c | 10 ++++++++++
 1 file changed, 10 insertions(+)
diff mbox

Patch

diff --git a/sound/soc/mxs/mxs-saif.c b/sound/soc/mxs/mxs-saif.c
index 1e724533dc6e..26c240af8099 100644
--- a/sound/soc/mxs/mxs-saif.c
+++ b/sound/soc/mxs/mxs-saif.c
@@ -309,6 +309,16 @@  static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
 		return -EBUSY;
 	}
 
+	/* If SAIF1 is configured as slave, the clk gate needs to be cleared
+	 * before the register can be written.
+	 */
+	if (saif->id != saif->master_id) {
+		__raw_writel(BM_SAIF_CTRL_SFTRST,
+			saif->base + SAIF_CTRL + MXS_CLR_ADDR);
+		__raw_writel(BM_SAIF_CTRL_CLKGATE,
+			saif->base + SAIF_CTRL + MXS_CLR_ADDR);
+	}
+
 	scr0 = __raw_readl(saif->base + SAIF_CTRL);
 	scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
 		& ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;