| Message ID | 20170117140230.23142-3-mylene.josserand@free-electrons.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
Hi, On Tue, Jan 17, 2017 at 03:02:22PM +0100, Mylène Josserand wrote: > The audio DAI needs to set the clock rates of the ac-dig clock. > To make it possible, the parent PLL audio clock rates should > also be changed. This is possible via "CLK_SET_RATE_PARENT" flag. > > Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> Please make sure to look at the prefixes usually used in the commit titles of the area you're working on. In this case that would have been "clk: sunxi-ng:". I fixed it, and applied. Thanks! Maxime
Hi, On 17/01/2017 17:44, Maxime Ripard wrote: > Hi, > > On Tue, Jan 17, 2017 at 03:02:22PM +0100, Mylène Josserand wrote: >> The audio DAI needs to set the clock rates of the ac-dig clock. >> To make it possible, the parent PLL audio clock rates should >> also be changed. This is possible via "CLK_SET_RATE_PARENT" flag. >> >> Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> > > Please make sure to look at the prefixes usually used in the commit > titles of the area you're working on. In this case that would have > been "clk: sunxi-ng:". I fixed it, and applied. Okay, I will pay more attention to prefixes for commit titles for next times. Thank you !
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c index 9bd1f78a0547..3cd4190ccd59 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c @@ -440,7 +440,7 @@ static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio", - 0x140, BIT(31), 0); + 0x140, BIT(31), CLK_SET_RATE_PARENT); static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x", 0x140, BIT(30), 0); static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
The audio DAI needs to set the clock rates of the ac-dig clock. To make it possible, the parent PLL audio clock rates should also be changed. This is possible via "CLK_SET_RATE_PARENT" flag. Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com> --- drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)