| Message ID | 20170129132444.25251-16-john@metanate.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Sun, Jan 29, 2017 at 01:24:35PM +0000, John Keeping wrote: > The bias, bandgap and PLL should all be configured before we enable > them. > Do you know why the test codes are hard-coded magic? It'd be nice to make some sense of them in a future patch. Reviewed-by: Sean Paul <seanpaul@chromium.org> > Signed-off-by: John Keeping <john@metanate.com> > --- > v3: > - Squash together two patches that both affect initialization order of > the PHY > Unchanged in v2 > > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 11 ++++++----- > 1 file changed, 6 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index 5b3068e9e8db..cfe7e4ba305c 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -413,12 +413,17 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) > > dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin)); > > - dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); > dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div)); > dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) | > LOW_PROGRAM_EN); > dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) | > HIGH_PROGRAM_EN); > + dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); > + > + dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN | > + BIASEXTR_SEL(BIASEXTR_127_7)); > + dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN | > + BANDGAP_SEL(BANDGAP_96_10)); > > dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT | > BIAS_BLOCK_ON | BANDGAP_ON); > @@ -429,10 +434,6 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) > SETRD_MAX | POWER_MANAGE | > TER_RESISTORS_ON); > > - dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN | > - BIASEXTR_SEL(BIASEXTR_127_7)); > - dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN | > - BANDGAP_SEL(BANDGAP_96_10)); > > dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf); > dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55); > -- > 2.11.0.197.gb556de5.dirty > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel
On Mon, 30 Jan 2017 15:28:08 -0500, Sean Paul wrote: > On Sun, Jan 29, 2017 at 01:24:35PM +0000, John Keeping wrote: > > The bias, bandgap and PLL should all be configured before we enable > > them. > > > > Do you know why the test codes are hard-coded magic? It'd be nice to make some > sense of them in a future patch. I just kept with the existing style of the code, but it should be straightforward to add some defines with sensible names. > Reviewed-by: Sean Paul <seanpaul@chromium.org> > > > Signed-off-by: John Keeping <john@metanate.com> > > --- > > v3: > > - Squash together two patches that both affect initialization order of > > the PHY > > Unchanged in v2 > > > > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 11 ++++++----- > > 1 file changed, 6 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > > index 5b3068e9e8db..cfe7e4ba305c 100644 > > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > > @@ -413,12 +413,17 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) > > > > dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin)); > > > > - dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); > > dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div)); > > dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) | > > LOW_PROGRAM_EN); > > dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) | > > HIGH_PROGRAM_EN); > > + dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); > > + > > + dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN | > > + BIASEXTR_SEL(BIASEXTR_127_7)); > > + dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN | > > + BANDGAP_SEL(BANDGAP_96_10)); > > > > dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT | > > BIAS_BLOCK_ON | BANDGAP_ON); > > @@ -429,10 +434,6 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) > > SETRD_MAX | POWER_MANAGE | > > TER_RESISTORS_ON); > > > > - dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN | > > - BIASEXTR_SEL(BIASEXTR_127_7)); > > - dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN | > > - BANDGAP_SEL(BANDGAP_96_10)); > > > > dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf); > > dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55); > > -- > > 2.11.0.197.gb556de5.dirty > > > > _______________________________________________ > > dri-devel mailing list > > dri-devel@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/dri-devel >
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c index 5b3068e9e8db..cfe7e4ba305c 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c @@ -413,12 +413,17 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin)); - dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div)); dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) | LOW_PROGRAM_EN); dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) | HIGH_PROGRAM_EN); + dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); + + dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN | + BIASEXTR_SEL(BIASEXTR_127_7)); + dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN | + BANDGAP_SEL(BANDGAP_96_10)); dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT | BIAS_BLOCK_ON | BANDGAP_ON); @@ -429,10 +434,6 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) SETRD_MAX | POWER_MANAGE | TER_RESISTORS_ON); - dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN | - BIASEXTR_SEL(BIASEXTR_127_7)); - dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN | - BANDGAP_SEL(BANDGAP_96_10)); dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf); dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55);
The bias, bandgap and PLL should all be configured before we enable them. Signed-off-by: John Keeping <john@metanate.com> --- v3: - Squash together two patches that both affect initialization order of the PHY Unchanged in v2 drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)