From patchwork Mon Mar 20 21:56:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnd Bergmann X-Patchwork-Id: 9635363 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 046E1601E9 for ; Mon, 20 Mar 2017 21:57:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DF12526E73 for ; Mon, 20 Mar 2017 21:57:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C171B2768C; Mon, 20 Mar 2017 21:57:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 36D5726E73 for ; Mon, 20 Mar 2017 21:57:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6835A6E0CC; Mon, 20 Mar 2017 21:57:35 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mout.kundenserver.de (mout.kundenserver.de [212.227.126.130]) by gabe.freedesktop.org (Postfix) with ESMTPS id D11F96E0CC; Mon, 20 Mar 2017 21:57:33 +0000 (UTC) Received: from wuerfel.lan ([78.42.17.5]) by mrelayeu.kundenserver.de (mreue003 [212.227.15.129]) with ESMTPA (Nemesis) id 0MWONS-1cfauZ0Dso-00XeMD; Mon, 20 Mar 2017 22:57:21 +0100 From: Arnd Bergmann To: Daniel Vetter , Jani Nikula , David Airlie Date: Mon, 20 Mar 2017 22:56:08 +0100 Message-Id: <20170320215713.3086140-1-arnd@arndb.de> X-Mailer: git-send-email 2.9.0 X-Provags-ID: V03:K0:xKRjt+q6H+fMgSvC5+7TNb5YVxQ1NsARJv6XaUVK6HrrW/RQXBo wKwd+aIacL0MR7yKGvrOh8Z8NcMytX1PlkYOuuecDBSU7NxRJNqzEgok27xWwJ5LnGg1RX9 a/x69vmlMg18/ut1t3tmc5eN7ykQsQd3EWwB042Syw6DL3IE5420VkjwszkQYdLBJuccjoM 0hTFoO5FJUcyh0RRPw0kA== X-UI-Out-Filterresults: notjunk:1; V01:K0:hKjtF3L/row=:NiGwr3saAQpUSFY2NfdBMV mIfFek/W7meVJphFSpSW3nesBzcA3S1hb53msRL3W/sTiJkvMAkAsmP/BoKc+1WqKW2FOrHwC aui9kSzTYQbuxwedkiNXN81YXneZKTeCf4R3t9ywy6ZLNOBFhrpYQtcuoGZTlUP6fxNm2LNEQ 4xzku438BEFpZK0B4txOVy5l8ayrq4NzpZQUAzWW3FRsaeoW6Sc0h0k5T9DEM+dl6y3lVLJEP oMdCQ3LGSFmpmXP6+vVaoMR+tZjWZQ6QmCZSLZeX+1rSUb+ipdW+3Uhhu8VcM1ku7kLkSWDh+ +BK3yO0HAmzfLd1UTmqpNZ6xh9Egi/RvU1koHhsgkM7tt1WpT59AYHSmbX+GF4ubbY0m9viTe WNtjGSymyw3aPwm0Siw2Wgob7W2tL4rJYVnJ20wzSSbMy/CvIjrkRRmWS1KEJSOdbT9TGrRkA d0dYDI5kHVjU+83JPUwsOUPAQvHMDDDpT3FxUWAWgHtz1hMb9xHvqvVnvuN7JgYHoxfE4F4dD tniB8rz5lwz5xxfjKI1Omf/GYpmcTYWUjB/fRQqRoodV8wpJelJibzXMvVmvlJOzMfNIQ2GlT qVYxcPDw/+7EnXSldNVQeiAnwYv9LfpYvevYX7BxnU64qXgiWCT8IZTW6O+axKyd5VbKE5SPg Xmvw2mwVbm/qO/fvN2wfpHPOw8D78YFnNLve47t1XpdbIaYXdUQslJs5YtrY7sTdmm+Q= Cc: Ander Conselvan de Oliveira , Arnd Bergmann , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Subject: [Intel-gfx] [PATCH] drm/i915: use static const array for PICK macro X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The varargs macro trick in _PIPE3/_PHY3/_PORT3 was meant as an optimization to shrink the i915 kernel module by around 1000 bytes. However, the downside is a size regression with CONFIG_KASAN, as I found from stack size warnings with gcc-7.0.1: before: drivers/gpu/drm/i915/intel_dpll_mgr.c: In function 'bxt_ddi_pll_get_hw_state': drivers/gpu/drm/i915/intel_dpll_mgr.c:1644:1: error: the frame size of 176 bytes is larger than 100 bytes [-Werror=frame-larger-than=] drivers/gpu/drm/i915/intel_dpll_mgr.c: In function 'bxt_ddi_pll_enable': drivers/gpu/drm/i915/intel_dpll_mgr.c:1548:1: error: the frame size of 224 bytes is larger than 100 bytes [-Werror=frame-larger-than=] after: drivers/gpu/drm/i915/intel_dpll_mgr.c: In function 'bxt_ddi_pll_get_hw_state': drivers/gpu/drm/i915/intel_dpll_mgr.c:1644:1: error: the frame size of 1016 bytes is larger than 1000 bytes [-Werror=frame-larger-than=] drivers/gpu/drm/i915/intel_dpll_mgr.c: In function 'bxt_ddi_pll_enable': drivers/gpu/drm/i915/intel_dpll_mgr.c:1548:1: error: the frame size of 1960 bytes is larger than 1000 bytes [-Werror=frame-larger-than=] I also checked the module sizes and got with gcc-7.0.1 original: text data bss dec hex filename 2380830 1155436 4448 3540714 3606ea drivers/gpu/drm/i915/i915-kasan.o 1298054 543692 2884 1844630 1c2596 drivers/gpu/drm/i915/i915-nokasan.o after ce64645d86ac: text data bss dec hex filename 2389515 1154476 4448 3548439 362517 drivers/gpu/drm/i915/i915-kasan.o 1299639 543692 2884 1846215 1c2bc7 drivers/gpu/drm/i915/i915-nokasan.o with this patch: text data bss dec hex filename 2381275 1163884 4448 3549607 3629a7 drivers/gpu/drm/i915/i915-kasan.o 1296038 543692 2884 1842614 1c1db6 drivers/gpu/drm/i915/i915-nokasan.o Actually showing a code size growth in .text both with and without kasan, and my version gets most of it back at the expense of larger .data when kasan is enabled. Fixes: ce64645d86ac ("drm/i915: use variadic macros and arrays to choose port/pipe based registers") Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=80114 Cc: Jani Nikula Signed-off-by: Arnd Bergmann --- drivers/gpu/drm/i915/i915_reg.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 04c8f69fcc62..39b53878a188 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -48,7 +48,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG); } -#define _PICK(__index, ...) (((const u32 []){ __VA_ARGS__ })[__index]) +#define _PICK(__index, ...) ({static const u32 __arr[] = { __VA_ARGS__ }; __arr[__index];}) #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) @@ -2657,10 +2657,10 @@ enum skl_disp_power_wells { /* * Clock control & power management */ -#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014) -#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018) -#define _CHV_DPLL_C (dev_priv->info.display_mmio_offset + 0x6030) -#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) +#define _DPLL_A 0x6014 +#define _DPLL_B 0x6018 +#define _CHV_DPLL_C 0x6030 +#define DPLL(pipe) _MMIO(dev_priv->info.display_mmio_offset + _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)) #define VGA0 _MMIO(0x6000) #define VGA1 _MMIO(0x6004) @@ -2756,10 +2756,10 @@ enum skl_disp_power_wells { #define SDVO_MULTIPLIER_SHIFT_HIRES 4 #define SDVO_MULTIPLIER_SHIFT_VGA 0 -#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c) -#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020) -#define _CHV_DPLL_C_MD (dev_priv->info.display_mmio_offset + 0x603c) -#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) +#define _DPLL_A_MD 0x601c +#define _DPLL_B_MD 0x6020 +#define _CHV_DPLL_C_MD 0x603c +#define DPLL_MD(pipe) _MMIO(dev_priv->info.display_mmio_offset + _PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD)) /* * UDI pixel divider, controlling how many pixels are stuffed into a packet.