From patchwork Wed Apr 26 18:34:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Garnier X-Patchwork-Id: 9701815 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9F41E6032C for ; Wed, 26 Apr 2017 18:35:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9518D28399 for ; Wed, 26 Apr 2017 18:35:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 88D75285F0; Wed, 26 Apr 2017 18:35:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from mother.openwall.net (mother.openwall.net [195.42.179.200]) by mail.wl.linuxfoundation.org (Postfix) with SMTP id 78B2128399 for ; Wed, 26 Apr 2017 18:35:12 +0000 (UTC) Received: (qmail 21515 invoked by uid 550); 26 Apr 2017 18:35:05 -0000 Mailing-List: contact kernel-hardening-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Delivered-To: mailing list kernel-hardening@lists.openwall.com Received: (qmail 20403 invoked from network); 26 Apr 2017 18:35:04 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=61krgMtvNaRWRZLyIWJZRY/J+qsCm/FWUZCuQqQ+p3Y=; b=FSpZzgoKLHOJM0t/2L1OxBJr7W6VspWHNKyv/+iVe011nKrJGTpFSmw8C/DhHc2w9O KFISOVrN1414K1Ar5+XaRLnoJqsG5yik3Pb2bsEMOsTiN0+59Db7fhtZs5l19DROnYDg nSRo7BL/JUVge80eoCI1uWX3GC6TIixYEcgFbV3uldt2+2/m6n1KSNNN2NY9a7l/pLvd m7B9qiTku7/DD4k/YqYGC82KpmQHalZq3WwF4StpZLbgJ/eqDUEvRG0eq1jQBbwNpg79 1cIYMPTEeffC/kHYPeZ+ACUoP1zL4WIc0HmH0vgVxplFsdF/VdEB6uqgJGzSudebnc8s vD2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=61krgMtvNaRWRZLyIWJZRY/J+qsCm/FWUZCuQqQ+p3Y=; b=JoWjpZpCBsc/O6FiXC11eG8z+CXqIglpIVu5dW/Z4LiAt17gIJpY6wiYU3R3aKnGg3 gcocGEAbHH2qy4+br3R3ZjDbc+0BTfoYmCFYgt2UxFdQHOPOeeNAlMA5FMVKodKSEllt 3ZtmjXTKfO8dDQ7U1TFm4NFLYlmHDHMyUty3JWu1cM3amrq9Yzz4l8yrSJiRBcLKRgM2 GXQgf2CB4zYUTUmR6bsNtoEmrvIkyk+dSkaA3MeBcahgji7zX1lhkKKELNAEuSf9Wvpm 5azqC4PTDAkm8lJW3KbcVRz+5WTpt/5yzEPGVMEDVGH6A2XScDPP43sSQwImTA4k/Gxr FTKw== X-Gm-Message-State: AN3rC/6gG2GIn+4fy1o1yabpCyZqWHq+xqvIDdDKyvOKh+JwuoDWH3wY yjnfwJA5SZQ6eA5W X-Received: by 10.99.0.79 with SMTP id 76mr1259974pga.119.1493231692051; Wed, 26 Apr 2017 11:34:52 -0700 (PDT) From: Thomas Garnier To: Martin Schwidefsky , Heiko Carstens , Dave Hansen , Arnd Bergmann , David Howells , =?UTF-8?q?Ren=C3=A9=20Nyffenegger?= , Thomas Garnier , Andrew Morton , "Paul E . McKenney" , Ingo Molnar , "Eric W . Biederman" , Thomas Gleixner , Oleg Nesterov , Pavel Tikhomirov , Ingo Molnar , "H . Peter Anvin" , Andy Lutomirski , Paolo Bonzini , Kees Cook , Rik van Riel , Josh Poimboeuf , Borislav Petkov , Brian Gerst , "Kirill A . Shutemov" , Christian Borntraeger , Russell King , Will Deacon , Catalin Marinas , Mark Rutland , James Morse Cc: linux-s390@vger.kernel.org, linux-kernel@vger.kernel.org, linux-api@vger.kernel.org, x86@kernel.org, linux-arm-kernel@lists.infradead.org, kernel-hardening@lists.openwall.com Date: Wed, 26 Apr 2017 11:34:23 -0700 Message-Id: <20170426183425.32158-2-thgarnie@google.com> X-Mailer: git-send-email 2.13.0.rc0.306.g87b477812d-goog In-Reply-To: <20170426183425.32158-1-thgarnie@google.com> References: <20170426183425.32158-1-thgarnie@google.com> Subject: [kernel-hardening] [PATCH v8 2/4] x86/syscalls: Optimize address limit check X-Virus-Scanned: ClamAV using ClamSMTP Disable the generic address limit check in favor of an architecture specific optimized implementation. The user-mode state check is added to the prepare_exit_to_usermode function. This function is called before any user-mode return on 32-bit and on the 64-bit syscall slowpath. For the 64-bit syscall fast path, an assembly address limit check redirects to the slow path if the address limit is different. The TASK_SIZE_MAX definition is moved to the pgtable_64_types header so it can be used in assembly code. Signed-off-by: Thomas Garnier --- Based on next-20170426 --- arch/x86/Kconfig | 1 + arch/x86/entry/common.c | 3 +++ arch/x86/entry/entry_64.S | 8 ++++++++ arch/x86/include/asm/pgtable_64_types.h | 11 +++++++++++ arch/x86/include/asm/processor.h | 11 ----------- 5 files changed, 23 insertions(+), 11 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index cd18994a9555..f3ce1859bd61 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -63,6 +63,7 @@ config X86 select ARCH_MIGHT_HAVE_ACPI_PDC if ACPI select ARCH_MIGHT_HAVE_PC_PARPORT select ARCH_MIGHT_HAVE_PC_SERIO + select ADDR_LIMIT_CHECK select ARCH_SUPPORTS_ATOMIC_RMW select ARCH_SUPPORTS_DEFERRED_STRUCT_PAGE_INIT select ARCH_SUPPORTS_NUMA_BALANCING if X86_64 diff --git a/arch/x86/entry/common.c b/arch/x86/entry/common.c index cdefcfdd9e63..057d133d7b78 100644 --- a/arch/x86/entry/common.c +++ b/arch/x86/entry/common.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include @@ -183,6 +184,8 @@ __visible inline void prepare_exit_to_usermode(struct pt_regs *regs) struct thread_info *ti = current_thread_info(); u32 cached_flags; + addr_limit_check_syscall(); + if (IS_ENABLED(CONFIG_PROVE_LOCKING) && WARN_ON(!irqs_disabled())) local_irq_disable(); diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S index 607d72c4a485..62aca6dcdaf4 100644 --- a/arch/x86/entry/entry_64.S +++ b/arch/x86/entry/entry_64.S @@ -218,6 +218,14 @@ entry_SYSCALL_64_fastpath: testl $_TIF_ALLWORK_MASK, TASK_TI_flags(%r11) jnz 1f + /* + * If address limit is not based on user-mode, jump to slow path for + * additional security checks. + */ + movq $TASK_SIZE_MAX, %rcx + cmp %rcx, TASK_addr_limit(%r11) + jne 1f + LOCKDEP_SYS_EXIT TRACE_IRQS_ON /* user mode is traced as IRQs on */ movq RIP(%rsp), %rcx diff --git a/arch/x86/include/asm/pgtable_64_types.h b/arch/x86/include/asm/pgtable_64_types.h index 06470da156ba..78af4d43a7ce 100644 --- a/arch/x86/include/asm/pgtable_64_types.h +++ b/arch/x86/include/asm/pgtable_64_types.h @@ -104,4 +104,15 @@ typedef struct { pteval_t pte; } pte_t; #define EARLY_DYNAMIC_PAGE_TABLES 64 +/* + * User space process size. 47bits minus one guard page. The guard + * page is necessary on Intel CPUs: if a SYSCALL instruction is at + * the highest possible canonical userspace address, then that + * syscall will enter the kernel with a non-canonical return + * address, and SYSRET will explode dangerously. We avoid this + * particular problem by preventing anything from being mapped + * at the maximum canonical address. + */ +#define TASK_SIZE_MAX ((_AC(1, UL) << 47) - PAGE_SIZE) + #endif /* _ASM_X86_PGTABLE_64_DEFS_H */ diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index 3cada998a402..e80822582d3e 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -825,17 +825,6 @@ static inline void spin_lock_prefetch(const void *x) #define KSTK_ESP(task) (task_pt_regs(task)->sp) #else -/* - * User space process size. 47bits minus one guard page. The guard - * page is necessary on Intel CPUs: if a SYSCALL instruction is at - * the highest possible canonical userspace address, then that - * syscall will enter the kernel with a non-canonical return - * address, and SYSRET will explode dangerously. We avoid this - * particular problem by preventing anything from being mapped - * at the maximum canonical address. - */ -#define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE) - /* This decides where the kernel will search for a free chunk of vm * space during mmap's. */