| Message ID | 20170508052434.3627-2-kai.huang@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 61eba9423b5c..e31c06ac3c65 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -292,6 +292,7 @@ #define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */ #define X86_FEATURE_LA57 (16*32+16) /* 5-level page tables */ #define X86_FEATURE_RDPID (16*32+22) /* RDPID instruction */ +#define X86_FEATURE_SGX_LAUNCH_CONTROL (16*32+30) /* SGX Launch Control */ /* AMD-defined CPU features, CPUID level 0x80000007 (ebx), word 17 */ #define X86_FEATURE_OVERFLOW_RECOV (17*32+0) /* MCA overflow recovery support */
For Intel CPU that supports SGX Launch Control, CPUID.0x7.0:ECX[bit 30] reports the availability of 1-setting of bit 17 of IA32_FEATURE_CONTROL MSR, which enables runtime configuration of SGX Launch Control via IA32_SGXLEPUBKEYHASHn. Signed-off-by: Kai Huang <kai.huang@linux.intel.com> --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+)