[07/10] render: Refactor to use newly shared pipeline setup code in i965_3d.c.

Message ID	1310678483-7494-8-git-send-email-kenneth@whitecape.org (mailing list archive)
State	New, archived
Headers	show Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.4) with ESMTP id p6ELSOhC019748 for <patchwork-intel-gfx@patchwork.kernel.org>; Thu, 14 Jul 2011 21:28:45 GMT DomainKey-Signature: a=rsa-sha1; c=nofws; d=whitecape.org; h=from:to:cc :subject:date:message-id:in-reply-to:references; q=dns; s= whitecape.org; b=t+2euH5Dl9Fi6qK69xamuiG/Lh5pvQjFVdKZEyAACOrNXtn mRz6C/+T4w49aSTarJFPb6/iAQJcK/8zt2tOsCcwmsWOMiCfBin29gkaOnIFqDKW 8d71rcXo4aV5XoR31AOSnrIRnMmpSf8VY3ElE+Syo5Km04HCrfYUrKmCD400= sender: kenneth@whitecape.org) by homiemail-a38.g.dreamhost.com (Postfix) with ESMTPSA id 4605210AFAA; Thu, 14 Jul 2011 14:24:34 -0700 (PDT) From: Kenneth Graunke <kenneth@whitecape.org> To: intel-gfx@lists.freedesktop.org Date: Thu, 14 Jul 2011 14:21:20 -0700 Message-Id: <1310678483-7494-8-git-send-email-kenneth@whitecape.org> In-Reply-To: <1310678483-7494-1-git-send-email-kenneth@whitecape.org> References: <1310678483-7494-1-git-send-email-kenneth@whitecape.org> Subject: [Intel-gfx] [PATCH 07/10] render: Refactor to use newly shared pipeline setup code in i965_3d.c. Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org

diff --git a/src/i965_3d.c b/src/i965_3d.c index 19ddee7..d4d38e5 100644 --- a/src/i965_3d.c +++ b/src/i965_3d.c @@ -130,11 +130,13 @@ void gen6_upload_cc_state_pointers(intel_screen_private *intel, drm_intel_bo *blend_bo, drm_intel_bo *cc_bo, - drm_intel_bo *depth_stencil_bo) + drm_intel_bo *depth_stencil_bo, + uint32_t blend_offset) { OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2)); if (blend_bo) - OUT_RELOC(blend_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); + OUT_RELOC(blend_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, + blend_offset | 1); else OUT_BATCH(0); @@ -153,11 +155,13 @@ void gen7_upload_cc_state_pointers(intel_screen_private *intel, drm_intel_bo *blend_bo, drm_intel_bo *cc_bo, - drm_intel_bo *depth_stencil_bo) + drm_intel_bo *depth_stencil_bo, + uint32_t blend_offset) { OUT_BATCH(GEN7_3DSTATE_BLEND_STATE_POINTERS | (2 - 2)); if (blend_bo) - OUT_RELOC(blend_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); + OUT_RELOC(blend_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, + blend_offset | 1); else OUT_BATCH(0); @@ -320,12 +324,14 @@ gen6_upload_clip_state(intel_screen_private *intel) } void -gen6_upload_sf_state(intel_screen_private *intel) +gen6_upload_sf_state(intel_screen_private *intel, + int num_sf_outputs, + int read_offset) { OUT_BATCH(GEN6_3DSTATE_SF | (20 - 2)); - OUT_BATCH((1 << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) | + OUT_BATCH((num_sf_outputs << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) | (1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) | - (0 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT)); + (read_offset << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT)); OUT_BATCH(0); OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE); OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */ @@ -347,12 +353,14 @@ gen6_upload_sf_state(intel_screen_private *intel) } void -gen7_upload_sf_state(intel_screen_private *intel) +gen7_upload_sf_state(intel_screen_private *intel, + int num_sf_outputs, + int read_offset) { OUT_BATCH(GEN7_3DSTATE_SBE | (14 - 2)); - OUT_BATCH((1 << GEN7_SBE_NUM_OUTPUTS_SHIFT) | + OUT_BATCH((num_sf_outputs << GEN7_SBE_NUM_OUTPUTS_SHIFT) | (1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT) | - (0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT)); + (read_offset << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT)); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); /* DW4 */ diff --git a/src/i965_render.c b/src/i965_render.c index c9b3c7a..17e35c9 100644 --- a/src/i965_render.c +++ b/src/i965_render.c @@ -2538,24 +2538,6 @@ gen6_composite_create_depth_stencil_state(intel_screen_private *intel) } static void -gen6_composite_invariant_states(intel_screen_private *intel) -{ - OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D); - - OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (3 - 2)); - OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER | - GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */ - OUT_BATCH(0); - - OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK | (2 - 2)); - OUT_BATCH(1); - - /* Set system instruction pointer */ - OUT_BATCH(BRW_STATE_SIP | 0); - OUT_BATCH(0); -} - -static void gen6_composite_state_base_address(intel_screen_private *intel) { OUT_BATCH(BRW_STATE_BASE_ADDRESS | (10 - 2)); @@ -2573,52 +2555,21 @@ gen6_composite_state_base_address(intel_screen_private *intel) } static void -gen6_composite_viewport_state_pointers(intel_screen_private *intel, - drm_intel_bo *cc_vp_bo) -{ - - OUT_BATCH(GEN6_3DSTATE_VIEWPORT_STATE_POINTERS | - GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC | - (4 - 2)); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_RELOC(cc_vp_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); -} - -static void -gen6_composite_urb(intel_screen_private *intel) -{ - OUT_BATCH(GEN6_3DSTATE_URB | (3 - 2)); - OUT_BATCH(((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) | - (24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */ - OUT_BATCH((0 << GEN6_3DSTATE_URB_GS_SIZE_SHIFT) | - (0 << GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT)); /* no GS thread */ -} - -static void gen6_composite_cc_state_pointers(intel_screen_private *intel, uint32_t blend_offset) { struct gen4_render_state *render_state = intel->gen4_render_state; + drm_intel_bo *cc_bo = NULL; + drm_intel_bo *depth_stencil_bo = NULL; if (intel->gen6_render_state.blend == blend_offset) return; - OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2)); - OUT_RELOC(render_state->gen6_blend_bo, - I915_GEM_DOMAIN_INSTRUCTION, 0, - blend_offset | 1); if (intel->gen6_render_state.blend == -1) { - OUT_RELOC(render_state->gen6_depth_stencil_bo, - I915_GEM_DOMAIN_INSTRUCTION, 0, - 1); - OUT_RELOC(render_state->cc_state_bo, - I915_GEM_DOMAIN_INSTRUCTION, 0, - 1); - } else { - OUT_BATCH(0); - OUT_BATCH(0); + cc_bo = render_state->cc_state_bo; + depth_stencil_bo = render_state->gen6_depth_stencil_bo; } + gen6_upload_cc_state_pointers(intel, render_state->gen6_blend_bo, cc_bo, depth_stencil_bo, blend_offset); intel->gen6_render_state.blend = blend_offset; } @@ -2632,49 +2583,7 @@ gen6_composite_sampler_state_pointers(intel_screen_private *intel, intel->gen6_render_state.samplers = bo; - OUT_BATCH(GEN6_3DSTATE_SAMPLER_STATE_POINTERS | - GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS | - (4 - 2)); - OUT_BATCH(0); /* VS */ - OUT_BATCH(0); /* GS */ - OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); -} - -static void -gen6_composite_vs_state(intel_screen_private *intel) -{ - /* disable VS constant buffer */ - OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | (5 - 2)); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - - OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2)); - OUT_BATCH(0); /* without VS kernel */ - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); /* pass-through */ -} - -static void -gen6_composite_gs_state(intel_screen_private *intel) -{ - /* disable GS constant buffer */ - OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (5 - 2)); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - - OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2)); - OUT_BATCH(0); /* without GS kernel */ - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); /* pass-through */ + gen6_upload_sampler_state_pointers(intel, bo); } static void @@ -2689,15 +2598,6 @@ gen6_composite_wm_constants(intel_screen_private *intel) } static void -gen6_composite_clip_state(intel_screen_private *intel) -{ - OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2)); - OUT_BATCH(0); - OUT_BATCH(0); /* pass-through */ - OUT_BATCH(0); -} - -static void gen6_composite_sf_state(intel_screen_private *intel, Bool has_mask) { @@ -2708,28 +2608,7 @@ gen6_composite_sf_state(intel_screen_private *intel, intel->gen6_render_state.num_sf_outputs = num_sf_outputs; - OUT_BATCH(GEN6_3DSTATE_SF | (20 - 2)); - OUT_BATCH((num_sf_outputs << GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT) | - (1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT) | - (1 << GEN6_3DSTATE_SF_URB_ENTRY_READ_OFFSET_SHIFT)); - OUT_BATCH(0); - OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE); - OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT); /* DW4 */ - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); /* DW9 */ - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); /* DW14 */ - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); /* DW19 */ + gen6_upload_sf_state(intel, num_sf_outputs, 1); } static void @@ -2763,35 +2642,6 @@ gen6_composite_wm_state(intel_screen_private *intel, } static void -gen6_composite_binding_table_pointers(intel_screen_private *intel) -{ - /* Binding table pointers */ - OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS | - GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS | - (4 - 2)); - OUT_BATCH(0); /* vs */ - OUT_BATCH(0); /* gs */ - /* Only the PS uses the binding table */ - OUT_BATCH(intel->surface_table); -} - -static void -gen6_composite_depth_buffer_state(intel_screen_private *intel) -{ - OUT_BATCH(BRW_3DSTATE_DEPTH_BUFFER | (7 - 2)); - OUT_BATCH((BRW_SURFACE_NULL << BRW_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT) | - (BRW_DEPTHFORMAT_D32_FLOAT << BRW_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT)); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - - OUT_BATCH(BRW_3DSTATE_CLEAR_PARAMS | (2 - 2)); - OUT_BATCH(0); -} - -static void gen6_composite_drawing_rectangle(intel_screen_private *intel, PixmapPtr dest) { @@ -2909,16 +2759,15 @@ gen6_emit_composite_state(struct intel_screen_private *intel) intel->needs_render_state_emit = FALSE; if (intel->needs_3d_invariant) { - gen6_composite_invariant_states(intel); - gen6_composite_viewport_state_pointers(intel, - render->cc_vp_bo); - gen6_composite_urb(intel); - - gen6_composite_vs_state(intel); - gen6_composite_gs_state(intel); - gen6_composite_clip_state(intel); + gen6_upload_invariant_states(intel); + gen6_upload_viewport_state_pointers(intel, render->cc_vp_bo); + gen6_upload_urb(intel); + + gen6_upload_vs_state(intel); + gen6_upload_gs_state(intel); + gen6_upload_clip_state(intel); gen6_composite_wm_constants(intel); - gen6_composite_depth_buffer_state(intel); + gen6_upload_depth_buffer_state(intel); intel->needs_3d_invariant = FALSE; } @@ -2938,7 +2787,7 @@ gen6_emit_composite_state(struct intel_screen_private *intel) gen6_composite_wm_state(intel, has_mask, render->wm_kernel_bo[composite_op->wm_kernel]); - gen6_composite_binding_table_pointers(intel); + gen6_upload_binding_table(intel, intel->surface_table); gen6_composite_drawing_rectangle(intel, intel->render_dest); gen6_composite_vertex_element_state(intel, has_mask, is_affine); diff --git a/src/i965_video.c b/src/i965_video.c index 7d7ac79..eb5ff14 100644 --- a/src/i965_video.c +++ b/src/i965_video.c @@ -1670,12 +1670,12 @@ gen6_emit_video_setup(ScrnInfoPtr scrn, gen6_upload_state_base_address(scrn, surface_state_binding_table_bo); gen6_upload_viewport_state_pointers(intel, intel->video.gen4_cc_vp_bo); gen6_upload_urb(intel); - gen6_upload_cc_state_pointers(intel, intel->video.gen6_blend_bo, intel->video.gen4_cc_bo, intel->video.gen6_depth_stencil_bo); + gen6_upload_cc_state_pointers(intel, intel->video.gen6_blend_bo, intel->video.gen4_cc_bo, intel->video.gen6_depth_stencil_bo, 0); gen6_upload_sampler_state_pointers(intel, intel->video.gen4_sampler_bo); gen6_upload_vs_state(intel); gen6_upload_gs_state(intel); gen6_upload_clip_state(intel); - gen6_upload_sf_state(intel); + gen6_upload_sf_state(intel, 1, 0); gen6_upload_wm_state(scrn, n_src_surf == 1 ? TRUE : FALSE); gen6_upload_binding_table(intel, (n_src_surf + 1) * SURFACE_STATE_PADDED_SIZE); gen6_upload_depth_buffer_state(intel); @@ -1779,12 +1779,12 @@ gen7_emit_video_setup(ScrnInfoPtr scrn, gen6_upload_state_base_address(scrn, surface_state_binding_table_bo); gen7_upload_viewport_state_pointers(intel, intel->video.gen4_cc_vp_bo); gen7_upload_urb(intel); - gen7_upload_cc_state_pointers(intel, intel->video.gen6_blend_bo, intel->video.gen4_cc_bo, intel->video.gen6_depth_stencil_bo); + gen7_upload_cc_state_pointers(intel, intel->video.gen6_blend_bo, intel->video.gen4_cc_bo, intel->video.gen6_depth_stencil_bo, 0); gen7_upload_sampler_state_pointers(intel, intel->video.gen4_sampler_bo); gen7_upload_bypass_states(intel); gen6_upload_vs_state(intel); gen6_upload_clip_state(intel); - gen7_upload_sf_state(intel); + gen7_upload_sf_state(intel, 1, 0); gen7_upload_wm_state(scrn, n_src_surf == 1 ? TRUE : FALSE); gen7_upload_binding_table(intel, (n_src_surf + 1) * SURFACE_STATE_PADDED_SIZE); gen7_upload_depth_buffer_state(intel); diff --git a/src/intel.h b/src/intel.h index 3f48dd4..42afaf4 100644 --- a/src/intel.h +++ b/src/intel.h @@ -607,10 +607,12 @@ void gen6_upload_urb(intel_screen_private *intel); void gen7_upload_urb(intel_screen_private *intel); void gen6_upload_cc_state_pointers(intel_screen_private *intel, drm_intel_bo *blend_bo, drm_intel_bo *cc_bo, - drm_intel_bo *depth_stencil_bo); + drm_intel_bo *depth_stencil_bo, + uint32_t blend_offset); void gen7_upload_cc_state_pointers(intel_screen_private *intel, drm_intel_bo *blend_bo, drm_intel_bo *cc_bo, - drm_intel_bo *depth_stencil_bo); + drm_intel_bo *depth_stencil_bo, + uint32_t blend_offset); void gen6_upload_sampler_state_pointers(intel_screen_private *intel, drm_intel_bo *sampler_bo); void gen7_upload_sampler_state_pointers(intel_screen_private *intel, @@ -619,8 +621,8 @@ void gen7_upload_bypass_states(intel_screen_private *intel); void gen6_upload_gs_state(intel_screen_private *intel); void gen6_upload_vs_state(intel_screen_private *intel); void gen6_upload_clip_state(intel_screen_private *intel); -void gen6_upload_sf_state(intel_screen_private *intel); -void gen7_upload_sf_state(intel_screen_private *intel); +void gen6_upload_sf_state(intel_screen_private *intel, int num_sf_outputs, int read_offset); +void gen7_upload_sf_state(intel_screen_private *intel, int num_sf_outputs, int read_offset); void gen6_upload_binding_table(intel_screen_private *intel, uint32_t ps_binding_table_offset); void gen7_upload_binding_table(intel_screen_private *intel, uint32_t ps_binding_table_offset); void gen6_upload_depth_buffer_state(intel_screen_private *intel);

[07/10] render: Refactor to use newly shared pipeline setup code in i965_3d.c.

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