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[97.113.165.157]) by smtp.gmail.com with ESMTPSA id m9sm60386qke.8.2017.06.08.22.36.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Jun 2017 22:36:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 8 Jun 2017 22:36:02 -0700 Message-Id: <20170609053611.26032-2-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170609053611.26032-1-rth@twiddle.net> References: <20170609053611.26032-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::243 Subject: [Qemu-devel] [PATCH 1/3] Guess L1 cache linesize for aarch64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, Marcus Shawcroft Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Using the cache hierarchy linesize minimum in CTR_EL0. See the comment within the code for rationale. * sysdeps/unix/sysv/linux/aarch64/sysconf.c: New file. Cc: Marcus Shawcroft --- sysdeps/unix/sysv/linux/aarch64/sysconf.c | 55 +++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 sysdeps/unix/sysv/linux/aarch64/sysconf.c diff --git a/sysdeps/unix/sysv/linux/aarch64/sysconf.c b/sysdeps/unix/sysv/linux/aarch64/sysconf.c new file mode 100644 index 0000000..30608dd --- /dev/null +++ b/sysdeps/unix/sysv/linux/aarch64/sysconf.c @@ -0,0 +1,55 @@ +/* Copyright (C) 2017 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library. If not, see + . */ + +#include +#include +#include +#include + + +static long int linux_sysconf (int name); + +/* Get the value of the system variable NAME. */ +long int +__sysconf (int name) +{ + unsigned ctr; + + /* Unfortunately, the registers that contain the actual cache info + (CCSIDR_EL1, CLIDR_EL1, and CSSELR_EL1) are protected by the Linux + kernel (though they need not have been). However, CTR_EL0 contains + the *minimum* linesize in the entire cache hierarchy, and is + accessible to userland, for use in __aarch64_sync_cache_range, + and it is a reasonable assumption that the L1 cache will have that + minimum line size. */ + switch (name) + { + case _SC_LEVEL1_ICACHE_LINESIZE: + asm("mrs\t%0, ctr_el0" : "=r"(ctr)); + return 4 << (ctr & 0xf); + case _SC_LEVEL1_DCACHE_LINESIZE: + asm("mrs\t%0, ctr_el0" : "=r"(ctr)); + return 4 << ((ctr >> 16) & 0xf); + } + + return linux_sysconf (name); +} + +/* Now the generic Linux version. */ +#undef __sysconf +#define __sysconf static linux_sysconf +#include