| Message ID | 1498063146-10802-1-git-send-email-anusha.srivatsa@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 06/21/2017 09:39 AM, Anusha Srivatsa wrote: > Add the PCI IDs for S SKU IN CFL by following the spec. > > v2: Update IDs. > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> > --- > intel/intel_chipset.h | 17 ++++++++++++++++- > 1 file changed, 16 insertions(+), 1 deletion(-) > > diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h > index 41fc0da..36bbec9 100644 > --- a/intel/intel_chipset.h > +++ b/intel/intel_chipset.h > @@ -221,6 +221,12 @@ > #define PCI_CHIP_GLK 0x3184 > #define PCI_CHIP_GLK_2X6 0x3185 > > +#define PCI_CHIP_COFFEELAKE_S_GT1_1 0x3E90 > +#define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93 > +#define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91 > +#define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92 > +#define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96 Matches BSPEC DID2 values. Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com> > + > #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ > (devid) == PCI_CHIP_I915_GM || \ > (devid) == PCI_CHIP_I945_GM || \ > @@ -452,10 +458,19 @@ > #define IS_GEMINILAKE(devid) ((devid) == PCI_CHIP_GLK || \ > (devid) == PCI_CHIP_GLK_2X6) > > +#define IS_CFL_S(devid) ((devid) == PCI_CHIP_COFFEELAKE_S_GT1_1 || \ > + (devid) == PCI_CHIP_COFFEELAKE_S_GT1_2 || \ > + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_1 || \ > + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \ > + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3 ) > + > +#define IS_COFFEELAKE(devid) (IS_CFL_S(devid)) > + > #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \ > IS_BROXTON(devid) || \ > IS_KABYLAKE(devid) || \ > - IS_GEMINILAKE(devid)) > + IS_GEMINILAKE(devid) || \ > + IS_COFFEELAKE(devid)) > > #define IS_9XX(dev) (IS_GEN3(dev) || \ > IS_GEN4(dev) || \
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 41fc0da..36bbec9 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -221,6 +221,12 @@ #define PCI_CHIP_GLK 0x3184 #define PCI_CHIP_GLK_2X6 0x3185 +#define PCI_CHIP_COFFEELAKE_S_GT1_1 0x3E90 +#define PCI_CHIP_COFFEELAKE_S_GT1_2 0x3E93 +#define PCI_CHIP_COFFEELAKE_S_GT2_1 0x3E91 +#define PCI_CHIP_COFFEELAKE_S_GT2_2 0x3E92 +#define PCI_CHIP_COFFEELAKE_S_GT2_3 0x3E96 + #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \ (devid) == PCI_CHIP_I915_GM || \ (devid) == PCI_CHIP_I945_GM || \ @@ -452,10 +458,19 @@ #define IS_GEMINILAKE(devid) ((devid) == PCI_CHIP_GLK || \ (devid) == PCI_CHIP_GLK_2X6) +#define IS_CFL_S(devid) ((devid) == PCI_CHIP_COFFEELAKE_S_GT1_1 || \ + (devid) == PCI_CHIP_COFFEELAKE_S_GT1_2 || \ + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_1 || \ + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_2 || \ + (devid) == PCI_CHIP_COFFEELAKE_S_GT2_3 ) + +#define IS_COFFEELAKE(devid) (IS_CFL_S(devid)) + #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \ IS_BROXTON(devid) || \ IS_KABYLAKE(devid) || \ - IS_GEMINILAKE(devid)) + IS_GEMINILAKE(devid) || \ + IS_COFFEELAKE(devid)) #define IS_9XX(dev) (IS_GEN3(dev) || \ IS_GEN4(dev) || \
Add the PCI IDs for S SKU IN CFL by following the spec. v2: Update IDs. Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com> --- intel/intel_chipset.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-)