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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id w69sm1883591pfk.107.2017.06.22.00.38.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 22 Jun 2017 00:39:01 -0700 (PDT) From: Bhupinder Thakur To: xen-devel@lists.xenproject.org Date: Thu, 22 Jun 2017 13:08:36 +0530 Message-Id: <1498117132-27139-2-git-send-email-bhupinder.thakur@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1498117132-27139-1-git-send-email-bhupinder.thakur@linaro.org> References: <1498117132-27139-1-git-send-email-bhupinder.thakur@linaro.org> Cc: Julien Grall , Stefano Stabellini Subject: [Xen-devel] [PATCH 01/17 v5] xen/arm: vpl011: Move vgic register access functions to vreg.h X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" X-Virus-Scanned: ClamAV using ClamSMTP These functions are generic in nature and can be reused by other emulation code in Xen. vGICv3 ITS and SBSA UART emulation code, would use these functions to operate on their registers. This patch moves the register access function definitions from vgic.h to vreg.h. Signed-off-by: Bhupinder Thakur Acked-by: Julien Grall --- CC: Stefano Stabellini CC: Julien Grall Changes since v3: - Moved the macro call VGIC_REG_HELPERS to vreg.h from vgic.h. xen/include/asm-arm/vgic.h | 111 +-------------------------------------------- xen/include/asm-arm/vreg.h | 110 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 111 insertions(+), 110 deletions(-) diff --git a/xen/include/asm-arm/vgic.h b/xen/include/asm-arm/vgic.h index 9ff713c..d4ed23d 100644 --- a/xen/include/asm-arm/vgic.h +++ b/xen/include/asm-arm/vgic.h @@ -20,6 +20,7 @@ #include #include +#include struct pending_irq { @@ -182,116 +183,6 @@ static inline int REG_RANK_NR(int b, uint32_t n) } } -#define VGIC_REG_MASK(size) ((~0UL) >> (BITS_PER_LONG - ((1 << (size)) * 8))) - -/* - * The check on the size supported by the register has to be done by - * the caller of vgic_regN_*. - * - * vgic_reg_* should never be called directly. Instead use the vgic_regN_* - * according to size of the emulated register - * - * Note that the alignment fault will always be taken in the guest - * (see B3.12.7 DDI0406.b). - */ -static inline register_t vgic_reg_extract(unsigned long reg, - unsigned int offset, - enum dabt_size size) -{ - reg >>= 8 * offset; - reg &= VGIC_REG_MASK(size); - - return reg; -} - -static inline void vgic_reg_update(unsigned long *reg, register_t val, - unsigned int offset, - enum dabt_size size) -{ - unsigned long mask = VGIC_REG_MASK(size); - int shift = offset * 8; - - *reg &= ~(mask << shift); - *reg |= ((unsigned long)val & mask) << shift; -} - -static inline void vgic_reg_setbits(unsigned long *reg, register_t bits, - unsigned int offset, - enum dabt_size size) -{ - unsigned long mask = VGIC_REG_MASK(size); - int shift = offset * 8; - - *reg |= ((unsigned long)bits & mask) << shift; -} - -static inline void vgic_reg_clearbits(unsigned long *reg, register_t bits, - unsigned int offset, - enum dabt_size size) -{ - unsigned long mask = VGIC_REG_MASK(size); - int shift = offset * 8; - - *reg &= ~(((unsigned long)bits & mask) << shift); -} - -/* N-bit register helpers */ -#define VGIC_REG_HELPERS(sz, offmask) \ -static inline register_t vgic_reg##sz##_extract(uint##sz##_t reg, \ - const mmio_info_t *info)\ -{ \ - return vgic_reg_extract(reg, info->gpa & offmask, \ - info->dabt.size); \ -} \ - \ -static inline void vgic_reg##sz##_update(uint##sz##_t *reg, \ - register_t val, \ - const mmio_info_t *info) \ -{ \ - unsigned long tmp = *reg; \ - \ - vgic_reg_update(&tmp, val, info->gpa & offmask, \ - info->dabt.size); \ - \ - *reg = tmp; \ -} \ - \ -static inline void vgic_reg##sz##_setbits(uint##sz##_t *reg, \ - register_t bits, \ - const mmio_info_t *info) \ -{ \ - unsigned long tmp = *reg; \ - \ - vgic_reg_setbits(&tmp, bits, info->gpa & offmask, \ - info->dabt.size); \ - \ - *reg = tmp; \ -} \ - \ -static inline void vgic_reg##sz##_clearbits(uint##sz##_t *reg, \ - register_t bits, \ - const mmio_info_t *info) \ -{ \ - unsigned long tmp = *reg; \ - \ - vgic_reg_clearbits(&tmp, bits, info->gpa & offmask, \ - info->dabt.size); \ - \ - *reg = tmp; \ -} - -/* - * 64 bits registers are only supported on platform with 64-bit long. - * This is also allow us to optimize the 32 bit case by using - * unsigned long rather than uint64_t - */ -#if BITS_PER_LONG == 64 -VGIC_REG_HELPERS(64, 0x7); -#endif -VGIC_REG_HELPERS(32, 0x3); - -#undef VGIC_REG_HELPERS - enum gic_sgi_mode; /* diff --git a/xen/include/asm-arm/vreg.h b/xen/include/asm-arm/vreg.h index ed2bd6f..348584f 100644 --- a/xen/include/asm-arm/vreg.h +++ b/xen/include/asm-arm/vreg.h @@ -107,4 +107,114 @@ static inline bool vreg_emulate_sysreg64(struct cpu_user_regs *regs, union hsr h #endif +#define VGIC_REG_MASK(size) ((~0UL) >> (BITS_PER_LONG - ((1 << (size)) * 8))) + +/* + * The check on the size supported by the register has to be done by + * the caller of vgic_regN_*. + * + * vgic_reg_* should never be called directly. Instead use the vgic_regN_* + * according to size of the emulated register + * + * Note that the alignment fault will always be taken in the guest + * (see B3.12.7 DDI0406.b). + */ +static inline register_t vgic_reg_extract(unsigned long reg, + unsigned int offset, + enum dabt_size size) +{ + reg >>= 8 * offset; + reg &= VGIC_REG_MASK(size); + + return reg; +} + +static inline void vgic_reg_update(unsigned long *reg, register_t val, + unsigned int offset, + enum dabt_size size) +{ + unsigned long mask = VGIC_REG_MASK(size); + int shift = offset * 8; + + *reg &= ~(mask << shift); + *reg |= ((unsigned long)val & mask) << shift; +} + +static inline void vgic_reg_setbits(unsigned long *reg, register_t bits, + unsigned int offset, + enum dabt_size size) +{ + unsigned long mask = VGIC_REG_MASK(size); + int shift = offset * 8; + + *reg |= ((unsigned long)bits & mask) << shift; +} + +static inline void vgic_reg_clearbits(unsigned long *reg, register_t bits, + unsigned int offset, + enum dabt_size size) +{ + unsigned long mask = VGIC_REG_MASK(size); + int shift = offset * 8; + + *reg &= ~(((unsigned long)bits & mask) << shift); +} + +/* N-bit register helpers */ +#define VGIC_REG_HELPERS(sz, offmask) \ +static inline register_t vgic_reg##sz##_extract(uint##sz##_t reg, \ + const mmio_info_t *info)\ +{ \ + return vgic_reg_extract(reg, info->gpa & offmask, \ + info->dabt.size); \ +} \ + \ +static inline void vgic_reg##sz##_update(uint##sz##_t *reg, \ + register_t val, \ + const mmio_info_t *info) \ +{ \ + unsigned long tmp = *reg; \ + \ + vgic_reg_update(&tmp, val, info->gpa & offmask, \ + info->dabt.size); \ + \ + *reg = tmp; \ +} \ + \ +static inline void vgic_reg##sz##_setbits(uint##sz##_t *reg, \ + register_t bits, \ + const mmio_info_t *info) \ +{ \ + unsigned long tmp = *reg; \ + \ + vgic_reg_setbits(&tmp, bits, info->gpa & offmask, \ + info->dabt.size); \ + \ + *reg = tmp; \ +} \ + \ +static inline void vgic_reg##sz##_clearbits(uint##sz##_t *reg, \ + register_t bits, \ + const mmio_info_t *info) \ +{ \ + unsigned long tmp = *reg; \ + \ + vgic_reg_clearbits(&tmp, bits, info->gpa & offmask, \ + info->dabt.size); \ + \ + *reg = tmp; \ +} + +/* + * 64 bits registers are only supported on platform with 64-bit long. + * This is also allow us to optimize the 32 bit case by using + * unsigned long rather than uint64_t + */ +#if BITS_PER_LONG == 64 +VGIC_REG_HELPERS(64, 0x7); +#endif +VGIC_REG_HELPERS(32, 0x3); + +#undef VGIC_REG_HELPERS + #endif /* __ASM_ARM_VREG__ */