[kvm-unit-tests,v1] s390x: add stidp interception test
diff mbox

Message ID 20170622075550.5307-1-david@redhat.com
State New
Headers show

Commit Message

David Hildenbrand June 22, 2017, 7:55 a.m. UTC
Let's add a test case for the STORE CPU ID instruction.

Signed-off-by: David Hildenbrand <david@redhat.com>
---
 lib/s390x/asm/arch_def.h |  8 ++++++++
 s390x/intercept.c        | 26 ++++++++++++++++++++++++++
 2 files changed, 34 insertions(+)

Comments

David Hildenbrand June 22, 2017, 7:58 a.m. UTC | #1
On 22.06.2017 09:55, David Hildenbrand wrote:
> Let's add a test case for the STORE CPU ID instruction.
> 
> Signed-off-by: David Hildenbrand <david@redhat.com>

Still tired, this is v2.

v1 -> v2:
- Simplified 0 checks in conditions (c == 0 -> !c)
- Use real text instead of copying conditions in reports
Thomas Huth June 22, 2017, 9:47 a.m. UTC | #2
On 22.06.2017 09:55, David Hildenbrand wrote:
> Let's add a test case for the STORE CPU ID instruction.
> 
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---
>  lib/s390x/asm/arch_def.h |  8 ++++++++
>  s390x/intercept.c        | 26 ++++++++++++++++++++++++++
>  2 files changed, 34 insertions(+)
> 
> diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h
> index 07d467e..72e5c60 100644
> --- a/lib/s390x/asm/arch_def.h
> +++ b/lib/s390x/asm/arch_def.h
> @@ -143,4 +143,12 @@ struct lowcore {
>  #define PGM_INT_CODE_CRYPTO_OPERATION		0x119
>  #define PGM_INT_CODE_TX_ABORTED_EVENT		0x200
>  
> +struct cpuid {
> +	uint64_t version : 8;
> +	uint64_t id : 24;
> +	uint64_t type : 16;
> +	uint64_t format : 1;
> +	uint64_t reserved : 15;
> +};
> +
>  #endif
> diff --git a/s390x/intercept.c b/s390x/intercept.c
> index 4558860..9766289 100644
> --- a/s390x/intercept.c
> +++ b/s390x/intercept.c
> @@ -105,6 +105,31 @@ static void test_stap(void)
>  	check_pgm_int_code(PGM_INT_CODE_ADDRESSING);
>  }
>  
> +/* Test the STORE CPU ID instruction */
> +static void test_stidp(void)
> +{
> +	struct cpuid id = {};
> +
> +	asm volatile ("stidp %0\n" : "+Q"(id));
> +	report("type set", id.type);
> +	report("version valid", !id.version || id.version == 0xff);
> +	report("reserved bits not set", !id.reserved);
> +
> +	expect_pgm_int();
> +	low_prot_enable();
> +	asm volatile ("stidp 0(%0)\n" : : "r"(8));
> +	low_prot_disable();
> +	check_pgm_int_code(PGM_INT_CODE_PROTECTION);
> +
> +	expect_pgm_int();
> +	asm volatile ("stidp 0(%0)\n" : : "r"(1));
> +	check_pgm_int_code(PGM_INT_CODE_SPECIFICATION);
> +
> +	expect_pgm_int();
> +	asm volatile ("stidp 0(%0)\n" : : "r"(-8));
> +	check_pgm_int_code(PGM_INT_CODE_ADDRESSING);
> +}
> +
>  /* Test the TEST BLOCK instruction */
>  static void test_testblock(void)
>  {
> @@ -152,6 +177,7 @@ struct {
>  	{ "stpx", test_stpx, false },
>  	{ "spx", test_spx, false },
>  	{ "stap", test_stap, false },
> +	{ "stidp", test_stidp, false },
>  	{ "testblock", test_testblock, false },
>  	{ NULL, NULL, false }
>  };
> 

Reviewed-by: Thomas Huth <thuth@redhat.com>
Radim Krčmář June 22, 2017, 12:20 p.m. UTC | #3
2017-06-22 09:55+0200, David Hildenbrand:
> Let's add a test case for the STORE CPU ID instruction.
> 
> Signed-off-by: David Hildenbrand <david@redhat.com>
> ---

Applied, thanks.

Patch
diff mbox

diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h
index 07d467e..72e5c60 100644
--- a/lib/s390x/asm/arch_def.h
+++ b/lib/s390x/asm/arch_def.h
@@ -143,4 +143,12 @@  struct lowcore {
 #define PGM_INT_CODE_CRYPTO_OPERATION		0x119
 #define PGM_INT_CODE_TX_ABORTED_EVENT		0x200
 
+struct cpuid {
+	uint64_t version : 8;
+	uint64_t id : 24;
+	uint64_t type : 16;
+	uint64_t format : 1;
+	uint64_t reserved : 15;
+};
+
 #endif
diff --git a/s390x/intercept.c b/s390x/intercept.c
index 4558860..9766289 100644
--- a/s390x/intercept.c
+++ b/s390x/intercept.c
@@ -105,6 +105,31 @@  static void test_stap(void)
 	check_pgm_int_code(PGM_INT_CODE_ADDRESSING);
 }
 
+/* Test the STORE CPU ID instruction */
+static void test_stidp(void)
+{
+	struct cpuid id = {};
+
+	asm volatile ("stidp %0\n" : "+Q"(id));
+	report("type set", id.type);
+	report("version valid", !id.version || id.version == 0xff);
+	report("reserved bits not set", !id.reserved);
+
+	expect_pgm_int();
+	low_prot_enable();
+	asm volatile ("stidp 0(%0)\n" : : "r"(8));
+	low_prot_disable();
+	check_pgm_int_code(PGM_INT_CODE_PROTECTION);
+
+	expect_pgm_int();
+	asm volatile ("stidp 0(%0)\n" : : "r"(1));
+	check_pgm_int_code(PGM_INT_CODE_SPECIFICATION);
+
+	expect_pgm_int();
+	asm volatile ("stidp 0(%0)\n" : : "r"(-8));
+	check_pgm_int_code(PGM_INT_CODE_ADDRESSING);
+}
+
 /* Test the TEST BLOCK instruction */
 static void test_testblock(void)
 {
@@ -152,6 +177,7 @@  struct {
 	{ "stpx", test_stpx, false },
 	{ "spx", test_spx, false },
 	{ "stap", test_stap, false },
+	{ "stidp", test_stidp, false },
 	{ "testblock", test_testblock, false },
 	{ NULL, NULL, false }
 };