diff mbox

[kvm-unit-tests] powerpc/sprs: Test POWER9 specific registers

Message ID 1499929407-29601-1-git-send-email-thuth@redhat.com (mailing list archive)
State New, archived
Headers show

Commit Message

Thomas Huth July 13, 2017, 7:03 a.m. UTC
Most of the SPRS are the same as on POWER8, so we can re-use
the PowerISA 2.07 functions and simply amend the additional
registers afterwards.

Signed-off-by: Thomas Huth <thuth@redhat.com>
---
 powerpc/sprs.c | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

Comments

Laurent Vivier July 21, 2017, 11:17 a.m. UTC | #1
On 13/07/2017 09:03, Thomas Huth wrote:
> Most of the SPRS are the same as on POWER8, so we can re-use
> the PowerISA 2.07 functions and simply amend the additional
> registers afterwards.
> 
> Signed-off-by: Thomas Huth <thuth@redhat.com>


Could you explain why you don't add 144 (TIDR)?

I don't see 813 and 814 in Power ISA
Version 3.0 B (March 29, 2017).

Thanks,
Laurent
> ---
>  powerpc/sprs.c | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/powerpc/sprs.c b/powerpc/sprs.c
> index 39644fa..73de2b6 100644
> --- a/powerpc/sprs.c
> +++ b/powerpc/sprs.c
> @@ -126,6 +126,17 @@ static void set_sprs_book3s_207(uint64_t val)
>  	mtspr(815, val);	/* TAR */
>  }
>  
> +/* SPRs from PowerISA 3.00 Book III */
> +static void set_sprs_book3s_300(uint64_t val)
> +{
> +	set_sprs_book3s_207(val);
> +	mtspr(48, val);		/* PIDR */
> +	mtspr(158, val);	/* GSR */
> +	mtspr(813, val);	/* LMRR */
> +	mtspr(814, val);	/* LMSER */
> +	mtspr(823, val);	/* PSSCR */
> +}
> +
>  static void set_sprs(uint64_t val)
>  {
>  	uint32_t pvr = mfspr(287);	/* Processor Version Register */
> @@ -143,6 +154,9 @@ static void set_sprs(uint64_t val)
>  	case 0x4d:			/* POWER8 */
>  		set_sprs_book3s_207(val);
>  		break;
> +	case 0x4e:			/* POWER9 */
> +		set_sprs_book3s_300(val);
> +		break;
>  	default:
>  		puts("Warning: Unknown processor version!\n");
>  	}
> @@ -218,6 +232,16 @@ static void get_sprs_book3s_207(uint64_t *v)
>  	v[815] = mfspr(815);	/* TAR */
>  }
>  
> +static void get_sprs_book3s_300(uint64_t *v)
> +{
> +	get_sprs_book3s_207(v);
> +	v[48] = mfspr(48);	/* PIDR */
> +	v[158] = mfspr(158);	/* GSR */
> +	v[813] = mfspr(813);	/* LMRR */
> +	v[814] = mfspr(814);	/* LMSER */
> +	v[823] = mfspr(823);	/* PSSCR */
> +}
> +
>  static void get_sprs(uint64_t *v)
>  {
>  	uint32_t pvr = mfspr(287);	/* Processor Version Register */
> @@ -235,6 +259,9 @@ static void get_sprs(uint64_t *v)
>  	case 0x4d:			/* POWER8 */
>  		get_sprs_book3s_207(v);
>  		break;
> +	case 0x4e:			/* POWER9 */
> +		get_sprs_book3s_300(v);
> +		break;
>  	}
>  }
>  
>
Thomas Huth July 21, 2017, 11:32 a.m. UTC | #2
On 21.07.2017 13:17, Laurent Vivier wrote:
> On 13/07/2017 09:03, Thomas Huth wrote:
>> Most of the SPRS are the same as on POWER8, so we can re-use
>> the PowerISA 2.07 functions and simply amend the additional
>> registers afterwards.
>>
>> Signed-off-by: Thomas Huth <thuth@redhat.com>
> 
> Could you explain why you don't add 144 (TIDR)?

Good catch. That register was not mentioned in the PowerISA version 3.0
A (from November 30, 2015) which I used when writing this patch.

> I don't see 813 and 814 in Power ISA
> Version 3.0 B (March 29, 2017).

They were mentioned in 3.0 A, but indeed seem to be gone in 3.0 B. I'll
update my patch accordingly...

Thanks for the review!

  Thomas
diff mbox

Patch

diff --git a/powerpc/sprs.c b/powerpc/sprs.c
index 39644fa..73de2b6 100644
--- a/powerpc/sprs.c
+++ b/powerpc/sprs.c
@@ -126,6 +126,17 @@  static void set_sprs_book3s_207(uint64_t val)
 	mtspr(815, val);	/* TAR */
 }
 
+/* SPRs from PowerISA 3.00 Book III */
+static void set_sprs_book3s_300(uint64_t val)
+{
+	set_sprs_book3s_207(val);
+	mtspr(48, val);		/* PIDR */
+	mtspr(158, val);	/* GSR */
+	mtspr(813, val);	/* LMRR */
+	mtspr(814, val);	/* LMSER */
+	mtspr(823, val);	/* PSSCR */
+}
+
 static void set_sprs(uint64_t val)
 {
 	uint32_t pvr = mfspr(287);	/* Processor Version Register */
@@ -143,6 +154,9 @@  static void set_sprs(uint64_t val)
 	case 0x4d:			/* POWER8 */
 		set_sprs_book3s_207(val);
 		break;
+	case 0x4e:			/* POWER9 */
+		set_sprs_book3s_300(val);
+		break;
 	default:
 		puts("Warning: Unknown processor version!\n");
 	}
@@ -218,6 +232,16 @@  static void get_sprs_book3s_207(uint64_t *v)
 	v[815] = mfspr(815);	/* TAR */
 }
 
+static void get_sprs_book3s_300(uint64_t *v)
+{
+	get_sprs_book3s_207(v);
+	v[48] = mfspr(48);	/* PIDR */
+	v[158] = mfspr(158);	/* GSR */
+	v[813] = mfspr(813);	/* LMRR */
+	v[814] = mfspr(814);	/* LMSER */
+	v[823] = mfspr(823);	/* PSSCR */
+}
+
 static void get_sprs(uint64_t *v)
 {
 	uint32_t pvr = mfspr(287);	/* Processor Version Register */
@@ -235,6 +259,9 @@  static void get_sprs(uint64_t *v)
 	case 0x4d:			/* POWER8 */
 		get_sprs_book3s_207(v);
 		break;
+	case 0x4e:			/* POWER9 */
+		get_sprs_book3s_300(v);
+		break;
 	}
 }