From patchwork Mon Jul 17 21:24:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 9846321 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 683B060392 for ; Mon, 17 Jul 2017 21:28:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9D46F26E4A for ; Mon, 17 Jul 2017 21:28:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 91FA7274D0; Mon, 17 Jul 2017 21:28:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D758926E4A for ; Mon, 17 Jul 2017 21:28:57 +0000 (UTC) Received: from localhost ([::1]:52645 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXDZZ-0001fK-4F for patchwork-qemu-devel@patchwork.kernel.org; Mon, 17 Jul 2017 17:28:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33558) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXDWO-0008D7-AA for qemu-devel@nongnu.org; Mon, 17 Jul 2017 17:25:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dXDWN-0003WI-6q for qemu-devel@nongnu.org; Mon, 17 Jul 2017 17:25:40 -0400 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:36274) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dXDWM-0003W3-TR for qemu-devel@nongnu.org; Mon, 17 Jul 2017 17:25:39 -0400 Received: by mail-qk0-x243.google.com with SMTP id d136so241783qkg.3 for ; Mon, 17 Jul 2017 14:25:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=u5lydVI+HJP71bYyz+LvB59pjBWxLzlTLdpOEK/X5Rg=; b=GNltgY7tO5Ihz7oWNcpBYZ8krYWh+DRcH8Xb7Yn2berlKbNFT4oXt/cU9jZHLS2AVB OeQZcjcOg2MPD2+AMk2Xoy/KBbbKhnxzgvllIdMaLBdBfu/3hIhin677HAQYi9YbH8vc KOtwrqq8xixp0jdvZA4Mo+KExAMBnu7cf7ZBUmAAYDty7kHoWg0CMJLP+TZYiAmy3hmD mjL0XEvXq6w+YdZMaO12pIekbRtiKGBzgj6YAhQBzloDPnqULN0HS63E1fsx3o4OMSwI z4VKJMi7f64f9yuFFn8QpPG15M740bN3zum3hREybgJTYKD6Hwfw0Lgr+a6/BnPCToGm /7dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=u5lydVI+HJP71bYyz+LvB59pjBWxLzlTLdpOEK/X5Rg=; b=hVF2z+p/K6oGFvF15sfy9aFbS59jquMV+HAqQgzMY+nKxU/CMexUse/SIuH0UBQ/4V 67h2WaMAh8uwjCS6Ia5+Z2PGXkE+KW+SHrnWYa23g/n/UHnUaTGk+Tg1D6bbQoutX/sa 8JvgxE8jMTZypb8OEYhH7lApLP12gsIPGT/l0FAayQ5zkLMO1vKTN7/OM2svVHMD2tWg g9yXgOwPGuCiWxfD8XUrGG5n0MNVh/k8ytysFwLR4E3eDkrIoX15NGEtUaUpMe5ctgF4 UTmJoyOOJ2qz9gJ4eFL8T9u9XR+pWwYEp5cJchjjSuVaWfvUWfJlZTyZ2jeEABZpD1D9 +gnA== X-Gm-Message-State: AIVw11389hfWKFoofj7oAVrb13DFoHCyRy7fOO03/io0prlytvpMoWRw csyynm9RmEXdnMUBm5s= X-Received: by 10.55.103.23 with SMTP id b23mr27905399qkc.55.1500326738126; Mon, 17 Jul 2017 14:25:38 -0700 (PDT) Received: from bigtime.com ([101.165.234.197]) by smtp.gmail.com with ESMTPSA id o20sm282034qtc.23.2017.07.17.14.25.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 17 Jul 2017 14:25:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 17 Jul 2017 11:24:43 -1000 Message-Id: <20170717212446.15268-6-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170717212446.15268-1-rth@twiddle.net> References: <20170717212446.15268-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PULL v2 5/8] target/s390x: Implement TRTR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Drop TRT from the set of insns handled internally by EXECUTE. It's more important to adjust the existing helper to handle both TRT and TRTR. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- target/s390x/helper.h | 1 + target/s390x/mem_helper.c | 20 +++++++++++++------- target/s390x/translate.c | 9 +++++++++ target/s390x/insn-data.def | 2 ++ 4 files changed, 25 insertions(+), 7 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 32314e0..4b02907 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -97,6 +97,7 @@ DEF_HELPER_FLAGS_3(tp, TCG_CALL_NO_WG, i32, env, i64, i32) DEF_HELPER_FLAGS_4(tr, TCG_CALL_NO_WG, void, env, i32, i64, i64) DEF_HELPER_4(tre, i64, env, i64, i64, i64) DEF_HELPER_4(trt, i32, env, i32, i64, i64) +DEF_HELPER_4(trtr, i32, env, i32, i64, i64) DEF_HELPER_5(trXX, i32, env, i32, i32, i32, i32) DEF_HELPER_4(cksm, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_5(calc_cc, TCG_CALL_NO_RWG_SE, i32, env, i32, i64, i64, i64) diff --git a/target/s390x/mem_helper.c b/target/s390x/mem_helper.c index 1926db7..cdc78aa 100644 --- a/target/s390x/mem_helper.c +++ b/target/s390x/mem_helper.c @@ -1277,17 +1277,18 @@ uint64_t HELPER(tre)(CPUS390XState *env, uint64_t array, return array + i; } -static uint32_t do_helper_trt(CPUS390XState *env, uint32_t len, uint64_t array, - uint64_t trans, uintptr_t ra) +static inline uint32_t do_helper_trt(CPUS390XState *env, int len, + uint64_t array, uint64_t trans, + int inc, uintptr_t ra) { - uint32_t i; + int i; for (i = 0; i <= len; i++) { - uint8_t byte = cpu_ldub_data_ra(env, array + i, ra); + uint8_t byte = cpu_ldub_data_ra(env, array + i * inc, ra); uint8_t sbyte = cpu_ldub_data_ra(env, trans + byte, ra); if (sbyte != 0) { - set_address(env, 1, array + i); + set_address(env, 1, array + i * inc); env->regs[2] = deposit64(env->regs[2], 0, 8, sbyte); return (i == len) ? 2 : 1; } @@ -1299,7 +1300,13 @@ static uint32_t do_helper_trt(CPUS390XState *env, uint32_t len, uint64_t array, uint32_t HELPER(trt)(CPUS390XState *env, uint32_t len, uint64_t array, uint64_t trans) { - return do_helper_trt(env, len, array, trans, GETPC()); + return do_helper_trt(env, len, array, trans, 1, GETPC()); +} + +uint32_t HELPER(trtr)(CPUS390XState *env, uint32_t len, uint64_t array, + uint64_t trans) +{ + return do_helper_trt(env, len, array, trans, -1, GETPC()); } /* Translate one/two to one/two */ @@ -2119,7 +2126,6 @@ void HELPER(ex)(CPUS390XState *env, uint32_t ilen, uint64_t r1, uint64_t addr) [0x6] = do_helper_oc, [0x7] = do_helper_xc, [0xc] = do_helper_tr, - [0xd] = do_helper_trt, }; dx_helper helper = dx[opc & 0xf]; diff --git a/target/s390x/translate.c b/target/s390x/translate.c index d83f2b9..b46f4c8 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -4447,6 +4447,15 @@ static ExitStatus op_trt(DisasContext *s, DisasOps *o) return NO_EXIT; } +static ExitStatus op_trtr(DisasContext *s, DisasOps *o) +{ + TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1)); + gen_helper_trtr(cc_op, cpu_env, l, o->addr1, o->in2); + tcg_temp_free_i32(l); + set_cc_static(s); + return NO_EXIT; +} + static ExitStatus op_trXX(DisasContext *s, DisasOps *o) { TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1)); diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index 1d34df03..ad84c74 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -916,6 +916,8 @@ C(0xdc00, TR, SS_a, Z, la1, a2, 0, 0, tr, 0) /* TRANSLATE AND TEST */ C(0xdd00, TRT, SS_a, Z, la1, a2, 0, 0, trt, 0) +/* TRANSLATE AND TEST REVERSE */ + C(0xd000, TRTR, SS_a, ETF3, la1, a2, 0, 0, trtr, 0) /* TRANSLATE EXTENDED */ C(0xb2a5, TRE, RRE, Z, 0, r2, r1_P, 0, tre, 0)