From patchwork Tue Jul 18 20:02:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 9849439 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 23F3F600CC for ; Tue, 18 Jul 2017 20:12:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F1175285A0 for ; Tue, 18 Jul 2017 20:12:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E603D285D9; Tue, 18 Jul 2017 20:12:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5A76F285A0 for ; Tue, 18 Jul 2017 20:12:22 +0000 (UTC) Received: from localhost ([::1]:58381 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXYqz-0005OD-Im for patchwork-qemu-devel@patchwork.kernel.org; Tue, 18 Jul 2017 16:12:21 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49833) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXYj9-0006Ux-Dj for qemu-devel@nongnu.org; Tue, 18 Jul 2017 16:04:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dXYj4-0004kf-OH for qemu-devel@nongnu.org; Tue, 18 Jul 2017 16:04:15 -0400 Received: from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:34582) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dXYj4-0004kR-Ju for qemu-devel@nongnu.org; Tue, 18 Jul 2017 16:04:10 -0400 Received: by mail-qk0-x243.google.com with SMTP id q66so3781018qki.1 for ; Tue, 18 Jul 2017 13:04:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=oca6lV09PUFtgktx6oK+8edzo9pvM1PZXXxvBSUaQjk=; b=o31WcxHfmKDo9SwrKImsA4zMuyNqQoeJLdIXj63hPKb7nQuZAJrV1n2i4AqzEiWTJ4 8umO+lcagedGdlXamndFDMKH051Dgv69ZnbmWz3HQsH+QqrRWXIhdjX/PoqcyxKQ48j7 dVczZolqH/OJyY3Y0RfdX2gW1qgLlZQ3zo2omiV5fyHuLI5TrGJpgs8jA5vxw30F1q2I TkMqDtiv+F1Yewhtf/ojGg+m7KKxTVGrW+0pYXZaKRmCt93Bti5uuXjVjLm+ou9VisOT /UzAikV/BQa1J6cf6orzfn6JZTP0Bzsfln/S6MK6XNdJLuCF/YaRvhjiw+8rs3MLxoYN rO5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=oca6lV09PUFtgktx6oK+8edzo9pvM1PZXXxvBSUaQjk=; b=jSkNrdYhQoVNhMeAKuTl/0Yt/dzGy01qedG1nmtlC5hRyz4UrBjHOup8Kvm+icn+MT VMElrVVL0UambZIzl8kjbTGQa2UiWg3cuFWfPdAPzJzM1KUHawfADOuN5YU2cN9PmOMd 34eA22WkiDwmgLBJHmcWMRlwUUzOyPD6bxqXc1Q7MdeDB2DswT4X/1E58GZ7e/oLtZve C6z7YWDsqniXAF4C9q0Am4UQSZAT2quBpxVqJwfg1zVkv0DdmtQZ8UCGAlyOx/tFKmHK tVBH8Ji995dZc1A9xcyNh6EDGeVA0Yg/ZqwqMpfRybW5sfHITRJic+Lzo9nbf56bAcB9 VUhA== X-Gm-Message-State: AIVw113ZwWFMM6YVw/cw3he6trFem96BYWmRav+A4h/5CXLXDbhA9lex CV9ZYx8RgJkiFLNqvxE= X-Received: by 10.233.220.195 with SMTP id q186mr4135671qkf.244.1500408249764; Tue, 18 Jul 2017 13:04:09 -0700 (PDT) Received: from bigtime.com ([101.165.234.197]) by smtp.gmail.com with ESMTPSA id b201sm2339817qkg.5.2017.07.18.13.04.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Jul 2017 13:04:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 18 Jul 2017 10:02:40 -1000 Message-Id: <20170718200255.31647-16-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170718200255.31647-1-rth@twiddle.net> References: <20170718200255.31647-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c09::243 Subject: [Qemu-devel] [PATCH v3 15/30] target/sh4: Merge DREG into fpr64 routines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP Also add a debugging assert that we did signal illegal opc for odd double-precision registers. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- target/sh4/translate.c | 26 +++++++++++++++----------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 019862d..9c320e4 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -339,11 +339,17 @@ static void gen_delayed_conditional_jump(DisasContext * ctx) static inline void gen_load_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { + /* We have already signaled illegal instruction for odd Dr. */ + tcg_debug_assert((reg & 1) == 0); + reg ^= ctx->fbank; tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]); } static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) { + /* We have already signaled illegal instruction for odd Dr. */ + tcg_debug_assert((reg & 1) == 0); + reg ^= ctx->fbank; tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fregs[reg], t); } @@ -362,8 +368,6 @@ static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg) #define FREG(x) cpu_fregs[(x) ^ ctx->fbank] #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) -/* Assumes lsb of (x) is always 0 */ -#define DREG(x) ((x) ^ ctx->fbank) #define CHECK_NOT_DELAY_SLOT \ if (ctx->envflags & DELAY_SLOT_MASK) { \ @@ -1094,8 +1098,8 @@ static void _decode_opc(DisasContext * ctx) break; /* illegal instruction */ fp0 = tcg_temp_new_i64(); fp1 = tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp0, DREG(B11_8)); - gen_load_fpr64(ctx, fp1, DREG(B7_4)); + gen_load_fpr64(ctx, fp0, B11_8); + gen_load_fpr64(ctx, fp1, B7_4); switch (ctx->opcode & 0xf00f) { case 0xf000: /* fadd Rm,Rn */ gen_helper_fadd_DT(fp0, cpu_env, fp0, fp1); @@ -1116,7 +1120,7 @@ static void _decode_opc(DisasContext * ctx) gen_helper_fcmp_gt_DT(cpu_sr_t, cpu_env, fp0, fp1); return; } - gen_store_fpr64(ctx, fp0, DREG(B11_8)); + gen_store_fpr64(ctx, fp0, B11_8); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); } else { @@ -1701,7 +1705,7 @@ static void _decode_opc(DisasContext * ctx) break; /* illegal instruction */ fp = tcg_temp_new_i64(); gen_helper_float_DT(fp, cpu_env, cpu_fpul); - gen_store_fpr64(ctx, fp, DREG(B11_8)); + gen_store_fpr64(ctx, fp, B11_8); tcg_temp_free_i64(fp); } else { @@ -1715,7 +1719,7 @@ static void _decode_opc(DisasContext * ctx) if (ctx->opcode & 0x0100) break; /* illegal instruction */ fp = tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp, DREG(B11_8)); + gen_load_fpr64(ctx, fp, B11_8); gen_helper_ftrc_DT(cpu_fpul, cpu_env, fp); tcg_temp_free_i64(fp); } @@ -1737,9 +1741,9 @@ static void _decode_opc(DisasContext * ctx) if (ctx->opcode & 0x0100) break; /* illegal instruction */ TCGv_i64 fp = tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp, DREG(B11_8)); + gen_load_fpr64(ctx, fp, B11_8); gen_helper_fsqrt_DT(fp, cpu_env, fp); - gen_store_fpr64(ctx, fp, DREG(B11_8)); + gen_store_fpr64(ctx, fp, B11_8); tcg_temp_free_i64(fp); } else { gen_helper_fsqrt_FT(FREG(B11_8), cpu_env, FREG(B11_8)); @@ -1765,7 +1769,7 @@ static void _decode_opc(DisasContext * ctx) { TCGv_i64 fp = tcg_temp_new_i64(); gen_helper_fcnvsd_FT_DT(fp, cpu_env, cpu_fpul); - gen_store_fpr64(ctx, fp, DREG(B11_8)); + gen_store_fpr64(ctx, fp, B11_8); tcg_temp_free_i64(fp); } return; @@ -1773,7 +1777,7 @@ static void _decode_opc(DisasContext * ctx) CHECK_FPU_ENABLED { TCGv_i64 fp = tcg_temp_new_i64(); - gen_load_fpr64(ctx, fp, DREG(B11_8)); + gen_load_fpr64(ctx, fp, B11_8); gen_helper_fcnvds_DT_FT(cpu_fpul, cpu_env, fp); tcg_temp_free_i64(fp); }