From patchwork Tue Jul 18 20:02:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 9849457 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 17E9F60392 for ; Tue, 18 Jul 2017 20:14:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E55A0201CB for ; Tue, 18 Jul 2017 20:14:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DA40F205F8; Tue, 18 Jul 2017 20:14:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 546C6201CB for ; Tue, 18 Jul 2017 20:14:56 +0000 (UTC) Received: from localhost ([::1]:58392 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXYtT-00089l-GY for patchwork-qemu-devel@patchwork.kernel.org; Tue, 18 Jul 2017 16:14:55 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49835) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dXYj9-0006Va-Ka for qemu-devel@nongnu.org; Tue, 18 Jul 2017 16:04:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dXYj6-0004lO-Ts for qemu-devel@nongnu.org; Tue, 18 Jul 2017 16:04:15 -0400 Received: from mail-qt0-x241.google.com ([2607:f8b0:400d:c0d::241]:34327) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dXYj6-0004lF-OD for qemu-devel@nongnu.org; Tue, 18 Jul 2017 16:04:12 -0400 Received: by mail-qt0-x241.google.com with SMTP id 19so3681847qty.1 for ; Tue, 18 Jul 2017 13:04:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=KTu75ZQYmkQrHGK/oeJhkklQ1gi+jnS27oG5NON8JW0=; b=NJZ3pMHT1Xv1gJKW3llIsEYDTP1xkAuPVUOt4r7KJBFpK73kBOUoAUv3Z6wpUBEMv7 U1G3GzDNmigm5kkZBq6m+pEQ2GFo4ZGKVia/P48PP7ZbCQZAOzmGKD8X/xG7Tt9yXs3F vewGF7pYybK1cNnl0+8MUL3iinKwOTXGm9eVLx+VPmE+w/25L6V73++FBl/jW/W9SHZa ww1qwA4GqMtMq5+fzsKOnHHRKddkZv3r4MlPq5yf9hSMh3xebhkbe6a8lbFF3Z8ULuue +sjYFGRz2UkmiJU+WeZeFXoxs4e/ycmG2nGlBOmV8OEPJvWXRe8ZnP8c1owaSlnCelxS IIJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=KTu75ZQYmkQrHGK/oeJhkklQ1gi+jnS27oG5NON8JW0=; b=hd4N272rUNI8QZ/mMoD9RHJWRrH09b6NyxR2BZdayVG3ouUYdU1UgS+gj2eIBYMOgQ Ub3r7zNGQFXoo/8RlzNupTR4tqpQb1V8+RUvdh1nlqDAFxyaYQ+2ThSO2ZL/g4v2XIS2 1GdDR4nt+w3RuQSAXx+oAmudTOnXY4tsJL+rEfXl/qZhjeXWujQBD3u5xLCuGOd6K4SD FB0+W+i3mbOROOVPQKqpfFqRLngspH1Uovhh9F1s59Uwf7xGzpFaRkneh2x9Tlokj0df YT0xHTyBgxv7Zbu556n+ukYBFo5lRM0j25YnQoaGq0sbtk2JXPbYtkzzd9cptG+Lo3L0 Y+lA== X-Gm-Message-State: AIVw111ufxTEXemRJ83hpHIkw8tUcsFAZDH7fkciScT9D/5UdE/bizoW aqFSpdFVRCYqz5+7qgk= X-Received: by 10.237.35.239 with SMTP id k44mr3977551qtc.125.1500408251914; Tue, 18 Jul 2017 13:04:11 -0700 (PDT) Received: from bigtime.com ([101.165.234.197]) by smtp.gmail.com with ESMTPSA id b201sm2339817qkg.5.2017.07.18.13.04.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Jul 2017 13:04:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 18 Jul 2017 10:02:41 -1000 Message-Id: <20170718200255.31647-17-rth@twiddle.net> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170718200255.31647-1-rth@twiddle.net> References: <20170718200255.31647-1-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400d:c0d::241 Subject: [Qemu-devel] [PATCH v3 16/30] target/sh4: Load/store Dr as 64-bit quantities X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aurelien@aurel32.net Errors-To: qemu-devel-bounces+patchwork-qemu-devel=patchwork.kernel.org@nongnu.org Sender: "Qemu-devel" X-Virus-Scanned: ClamAV using ClamSMTP This enforces proper alignment and makes the register update more natural. Note that there is a more serious bug fix for fmov {DX}Rn,@(R0,Rn) to use a store instead of a load. Signed-off-by: Richard Henderson --- V2: Fix pre-dec address error. --- target/sh4/translate.c | 75 ++++++++++++++++++++++++-------------------------- 1 file changed, 36 insertions(+), 39 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 9c320e4..bda6fa7 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -998,12 +998,10 @@ static void _decode_opc(DisasContext * ctx) case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { - TCGv addr_hi = tcg_temp_new(); - int fr = XHACK(B7_4); - tcg_gen_addi_i32(addr_hi, REG(B11_8), 4); - tcg_gen_qemu_st_i32(FREG(fr), REG(B11_8), ctx->memidx, MO_TEUL); - tcg_gen_qemu_st_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEUL); - tcg_temp_free(addr_hi); + TCGv_i64 fp = tcg_temp_new_i64(); + gen_load_fpr64(ctx, fp, XHACK(B7_4)); + tcg_gen_qemu_st_i64(fp, REG(B11_8), ctx->memidx, MO_TEQ); + tcg_temp_free_i64(fp); } else { tcg_gen_qemu_st_i32(FREG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL); } @@ -1011,12 +1009,10 @@ static void _decode_opc(DisasContext * ctx) case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { - TCGv addr_hi = tcg_temp_new(); - int fr = XHACK(B11_8); - tcg_gen_addi_i32(addr_hi, REG(B7_4), 4); - tcg_gen_qemu_ld_i32(FREG(fr), REG(B7_4), ctx->memidx, MO_TEUL); - tcg_gen_qemu_ld_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEUL); - tcg_temp_free(addr_hi); + TCGv_i64 fp = tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(fp, REG(B7_4), ctx->memidx, MO_TEQ); + gen_store_fpr64(ctx, fp, XHACK(B11_8)); + tcg_temp_free_i64(fp); } else { tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TEUL); } @@ -1024,13 +1020,11 @@ static void _decode_opc(DisasContext * ctx) case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED if (ctx->tbflags & FPSCR_SZ) { - TCGv addr_hi = tcg_temp_new(); - int fr = XHACK(B11_8); - tcg_gen_addi_i32(addr_hi, REG(B7_4), 4); - tcg_gen_qemu_ld_i32(FREG(fr), REG(B7_4), ctx->memidx, MO_TEUL); - tcg_gen_qemu_ld_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEUL); - tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8); - tcg_temp_free(addr_hi); + TCGv_i64 fp = tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(fp, REG(B7_4), ctx->memidx, MO_TEQ); + gen_store_fpr64(ctx, fp, XHACK(B11_8)); + tcg_temp_free_i64(fp); + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8); } else { tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TEUL); tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); @@ -1038,18 +1032,21 @@ static void _decode_opc(DisasContext * ctx) return; case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ CHECK_FPU_ENABLED - TCGv addr = tcg_temp_new_i32(); - tcg_gen_subi_i32(addr, REG(B11_8), 4); - if (ctx->tbflags & FPSCR_SZ) { - int fr = XHACK(B7_4); - tcg_gen_qemu_st_i32(FREG(fr + 1), addr, ctx->memidx, MO_TEUL); - tcg_gen_subi_i32(addr, addr, 4); - tcg_gen_qemu_st_i32(FREG(fr), addr, ctx->memidx, MO_TEUL); - } else { - tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL); - } - tcg_gen_mov_i32(REG(B11_8), addr); - tcg_temp_free(addr); + { + TCGv addr = tcg_temp_new_i32(); + if (ctx->tbflags & FPSCR_SZ) { + TCGv_i64 fp = tcg_temp_new_i64(); + gen_load_fpr64(ctx, fp, XHACK(B7_4)); + tcg_gen_subi_i32(addr, REG(B11_8), 8); + tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, MO_TEQ); + tcg_temp_free_i64(fp); + } else { + tcg_gen_subi_i32(addr, REG(B11_8), 4); + tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL); + } + tcg_gen_mov_i32(REG(B11_8), addr); + tcg_temp_free(addr); + } return; case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ CHECK_FPU_ENABLED @@ -1057,10 +1054,10 @@ static void _decode_opc(DisasContext * ctx) TCGv addr = tcg_temp_new_i32(); tcg_gen_add_i32(addr, REG(B7_4), REG(0)); if (ctx->tbflags & FPSCR_SZ) { - int fr = XHACK(B11_8); - tcg_gen_qemu_ld_i32(FREG(fr), addr, ctx->memidx, MO_TEUL); - tcg_gen_addi_i32(addr, addr, 4); - tcg_gen_qemu_ld_i32(FREG(fr + 1), addr, ctx->memidx, MO_TEUL); + TCGv_i64 fp = tcg_temp_new_i64(); + tcg_gen_qemu_ld_i64(fp, addr, ctx->memidx, MO_TEQ); + gen_store_fpr64(ctx, fp, XHACK(B11_8)); + tcg_temp_free_i64(fp); } else { tcg_gen_qemu_ld_i32(FREG(B11_8), addr, ctx->memidx, MO_TEUL); } @@ -1073,10 +1070,10 @@ static void _decode_opc(DisasContext * ctx) TCGv addr = tcg_temp_new(); tcg_gen_add_i32(addr, REG(B11_8), REG(0)); if (ctx->tbflags & FPSCR_SZ) { - int fr = XHACK(B7_4); - tcg_gen_qemu_ld_i32(FREG(fr), addr, ctx->memidx, MO_TEUL); - tcg_gen_addi_i32(addr, addr, 4); - tcg_gen_qemu_ld_i32(FREG(fr + 1), addr, ctx->memidx, MO_TEUL); + TCGv_i64 fp = tcg_temp_new_i64(); + gen_load_fpr64(ctx, fp, XHACK(B7_4)); + tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, MO_TEQ); + tcg_temp_free_i64(fp); } else { tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL); }