[v6,7/7] drm/rockchip: vop: rk3328: fix overlay abnormal
diff mbox

Message ID 1501049980-6239-1-git-send-email-mark.yao@rock-chips.com
State New
Headers show

Commit Message

yao mark July 26, 2017, 6:19 a.m. UTC
It's a hardware bug, all window's overlay channel reset
value is same, hardware overlay would be die.

so we must initial difference id for each overlay channel.

The Channel register is supported on all vop will full design.
Following is the details for this register
VOP_WIN0_CTRL2
  bit[7:4] win_rid_win0_cbr
       axi read id of win0 cbr channel
  bit[3:0] win_rid_win0_yrgb
       axi read id of win0 yrgb channel

Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 2 ++
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 1 +
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 1 +
 3 files changed, 4 insertions(+)

Comments

JeffyChen July 27, 2017, 8:42 a.m. UTC | #1
Hi mark,

On 07/26/2017 02:19 PM, Mark yao wrote:
> It's a hardware bug, all window's overlay channel reset
> value is same, hardware overlay would be die.
>
> so we must initial difference id for each overlay channel.
>
> The Channel register is supported on all vop will full design.
> Following is the details for this register
> VOP_WIN0_CTRL2
>    bit[7:4] win_rid_win0_cbr
>         axi read id of win0 cbr channel
>    bit[3:0] win_rid_win0_yrgb
>         axi read id of win0 yrgb channel
>
> Signed-off-by: Mark Yao<mark.yao@rock-chips.com>

Reviewed-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Heiko Stuebner July 28, 2017, 1:06 p.m. UTC | #2
Am Mittwoch, 26. Juli 2017, 14:19:39 CEST schrieb Mark Yao:
> It's a hardware bug, all window's overlay channel reset
> value is same, hardware overlay would be die.
> 
> so we must initial difference id for each overlay channel.
> 
> The Channel register is supported on all vop will full design.
> Following is the details for this register
> VOP_WIN0_CTRL2
>   bit[7:4] win_rid_win0_cbr
>        axi read id of win0 cbr channel
>   bit[3:0] win_rid_win0_yrgb
>        axi read id of win0 yrgb channel
> 
> Signed-off-by: Mark Yao <mark.yao@rock-chips.com>

rk3036 and rk3288 are not negatively affected by this, so
on rk3036 and rk3288
Tested-by: Heiko Stuebner <heiko@sntech.de>

Patch
diff mbox

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 92d098b..e4b3388 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1452,7 +1452,9 @@  static int vop_initial(struct vop *vop)
 
 	for (i = 0; i < vop_data->win_size; i++) {
 		const struct vop_win_data *win = &vop_data->win[i];
+		int channel = i * 2 + 1;
 
+		VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
 		VOP_WIN_SET(vop, win, enable, 0);
 		VOP_WIN_SET(vop, win, gate, 1);
 	}
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 43d08c8..af1091f 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -141,6 +141,7 @@  struct vop_win_phy {
 
 	struct vop_reg dst_alpha_ctl;
 	struct vop_reg src_alpha_ctl;
+	struct vop_reg channel;
 };
 
 struct vop_win_data {
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index bc7b2d0..94de7b9 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -197,6 +197,7 @@ 
 	.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
 	.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
 	.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
+	.channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
 };
 
 static const struct vop_win_phy rk3288_win23_data = {