[RFC,02/12] clk: qcom: flag for 64 bit CONFIG_CTL
diff mbox

Message ID 1501153825-5181-3-git-send-email-absahu@codeaurora.org
State Superseded
Delegated to: Stephen Boyd
Headers show

Commit Message

Abhishek Sahu July 27, 2017, 11:10 a.m. UTC
Some of the Alpha PLL’s (like Spark, Brammo PLL) do not have
CONFIG_CTL_U register. This patch adds the flag for PLL’s
which have CONFIG_CTL_U register and checks the same while
doing PLL initial configuration.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
---
 drivers/clk/qcom/clk-alpha-pll.c | 5 ++++-
 drivers/clk/qcom/clk-alpha-pll.h | 7 ++++---
 2 files changed, 8 insertions(+), 4 deletions(-)

Comments

Stephen Boyd July 28, 2017, 6:33 p.m. UTC | #1
On 07/27, Abhishek Sahu wrote:
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 47a1da3..e6cde2d 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -118,7 +118,10 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>  	regmap_write(regmap, off + PLL_L_VAL, config->l);
>  	regmap_write(regmap, off + PLL_ALPHA_VAL, config->alpha);
>  	regmap_write(regmap, off + PLL_CONFIG_CTL, config->config_ctl_val);
> -	regmap_write(regmap, off + PLL_CONFIG_CTL_U, config->config_ctl_hi_val);
> +
> +	if (pll->flags & SUPPORTS_64BIT_CONFIG_CTL)
> +		regmap_write(regmap, off + PLL_CONFIG_CTL_U,
> +			     config->config_ctl_hi_val);

Is there a hole there? I mean a RAZ/WI register so we can just
keep writing it and not care?
Abhishek Sahu July 30, 2017, 1:04 p.m. UTC | #2
On 2017-07-29 00:03, Stephen Boyd wrote:
> On 07/27, Abhishek Sahu wrote:
>> diff --git a/drivers/clk/qcom/clk-alpha-pll.c 
>> b/drivers/clk/qcom/clk-alpha-pll.c
>> index 47a1da3..e6cde2d 100644
>> --- a/drivers/clk/qcom/clk-alpha-pll.c
>> +++ b/drivers/clk/qcom/clk-alpha-pll.c
>> @@ -118,7 +118,10 @@ void clk_alpha_pll_configure(struct clk_alpha_pll 
>> *pll, struct regmap *regmap,
>>  	regmap_write(regmap, off + PLL_L_VAL, config->l);
>>  	regmap_write(regmap, off + PLL_ALPHA_VAL, config->alpha);
>>  	regmap_write(regmap, off + PLL_CONFIG_CTL, config->config_ctl_val);
>> -	regmap_write(regmap, off + PLL_CONFIG_CTL_U, 
>> config->config_ctl_hi_val);
>> +
>> +	if (pll->flags & SUPPORTS_64BIT_CONFIG_CTL)
>> +		regmap_write(regmap, off + PLL_CONFIG_CTL_U,
>> +			     config->config_ctl_hi_val);
> 
> Is there a hole there? I mean a RAZ/WI register so we can just
> keep writing it and not care?

  We don't have hole for most of the alpha PLL. The offset for
  CONFIG_CTL itself is not same for all types of Alpha PLL
  and the same is being handled in patch 4 of this patch
  series.

  Spark PLL
  CONFIG_CTL	0x18
  TEST_CTL	0x1C
  TEST_CTL_U	0x20

  Brammo PLL
  CONFIG_CTL	0x18
  TEST_CTL	0x1C
  PLL_STATUS     0x24

  Hyuara PLL
  CONFIG_CTL	0x14
  CONFIG_CTL_U	0x18
  TEST_CTL       0x1c
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Stephen Boyd Aug. 1, 2017, 9:17 p.m. UTC | #3
On 07/30, Abhishek Sahu wrote:
> On 2017-07-29 00:03, Stephen Boyd wrote:
> >On 07/27, Abhishek Sahu wrote:
> >>diff --git a/drivers/clk/qcom/clk-alpha-pll.c
> >>b/drivers/clk/qcom/clk-alpha-pll.c
> >>index 47a1da3..e6cde2d 100644
> >>--- a/drivers/clk/qcom/clk-alpha-pll.c
> >>+++ b/drivers/clk/qcom/clk-alpha-pll.c
> >>@@ -118,7 +118,10 @@ void clk_alpha_pll_configure(struct
> >>clk_alpha_pll *pll, struct regmap *regmap,
> >> 	regmap_write(regmap, off + PLL_L_VAL, config->l);
> >> 	regmap_write(regmap, off + PLL_ALPHA_VAL, config->alpha);
> >> 	regmap_write(regmap, off + PLL_CONFIG_CTL, config->config_ctl_val);
> >>-	regmap_write(regmap, off + PLL_CONFIG_CTL_U,
> >>config->config_ctl_hi_val);
> >>+
> >>+	if (pll->flags & SUPPORTS_64BIT_CONFIG_CTL)
> >>+		regmap_write(regmap, off + PLL_CONFIG_CTL_U,
> >>+			     config->config_ctl_hi_val);
> >
> >Is there a hole there? I mean a RAZ/WI register so we can just
> >keep writing it and not care?
> 
>  We don't have hole for most of the alpha PLL. The offset for
>  CONFIG_CTL itself is not same for all types of Alpha PLL
>  and the same is being handled in patch 4 of this patch
>  series.
> 
>  Spark PLL
>  CONFIG_CTL	0x18
>  TEST_CTL	0x1C
>  TEST_CTL_U	0x20
> 
>  Brammo PLL
>  CONFIG_CTL	0x18
>  TEST_CTL	0x1C
>  PLL_STATUS     0x24
> 
>  Hyuara PLL
>  CONFIG_CTL	0x14
>  CONFIG_CTL_U	0x18
>  TEST_CTL       0x1c

Ok. Thanks for checking.

Patch
diff mbox

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 47a1da3..e6cde2d 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -118,7 +118,10 @@  void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 	regmap_write(regmap, off + PLL_L_VAL, config->l);
 	regmap_write(regmap, off + PLL_ALPHA_VAL, config->alpha);
 	regmap_write(regmap, off + PLL_CONFIG_CTL, config->config_ctl_val);
-	regmap_write(regmap, off + PLL_CONFIG_CTL_U, config->config_ctl_hi_val);
+
+	if (pll->flags & SUPPORTS_64BIT_CONFIG_CTL)
+		regmap_write(regmap, off + PLL_CONFIG_CTL_U,
+			     config->config_ctl_hi_val);
 
 	val = config->main_output_mask;
 	val |= config->aux_output_mask;
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
index d6e1ee2..bbd6aa9 100644
--- a/drivers/clk/qcom/clk-alpha-pll.h
+++ b/drivers/clk/qcom/clk-alpha-pll.h
@@ -34,9 +34,10 @@  struct clk_alpha_pll {
 
 	const struct pll_vco *vco_table;
 	size_t num_vco;
-#define SUPPORTS_OFFLINE_REQ	BIT(0)
-#define SUPPORTS_16BIT_ALPHA	BIT(1)
-#define SUPPORTS_FSM_MODE	BIT(2)
+#define SUPPORTS_OFFLINE_REQ		BIT(0)
+#define SUPPORTS_16BIT_ALPHA		BIT(1)
+#define SUPPORTS_FSM_MODE		BIT(2)
+#define SUPPORTS_64BIT_CONFIG_CTL	BIT(3)
 	u8 flags;
 
 	struct clk_regmap clkr;