Patchwork [5/8] drm/exynos: introduce BYTE_PITCH capability

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Submitter Tobias Jakobi
Date Aug. 9, 2017, 11:48 a.m.
Message ID <20170809114857.4945-6-tjakobi@math.uni-bielefeld.de>
Download mbox | patch
Permalink /patch/9890415/
State New
Headers show

Comments

Tobias Jakobi - Aug. 9, 2017, 11:48 a.m.
In some of drivers we compute something like 'pitch / cpp' at some
point, silently assuming that the pitch (which is in bytes) is
divisible by the buffer's cpp. This is not always true, in particular
DRM core does not check for pitch alignment in the common case.

Introduce a new cap which indicates that the hardware supports a
pitch with 'byte-granularity'. If the cap is not set, assume that
we need pitch aligned to cpp.

We set this cap later for the drivers/planes that support it.

Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
---
 drivers/gpu/drm/exynos/exynos_drm_drv.h   |  1 +
 drivers/gpu/drm/exynos/exynos_drm_plane.c | 10 ++++++++++
 2 files changed, 11 insertions(+)
Inki Dae - Aug. 11, 2017, 8:23 a.m.
2017년 08월 09일 20:48에 Tobias Jakobi 이(가) 쓴 글:
> In some of drivers we compute something like 'pitch / cpp' at some
> point, silently assuming that the pitch (which is in bytes) is
> divisible by the buffer's cpp. This is not always true, in particular
> DRM core does not check for pitch alignment in the common case.
> 
> Introduce a new cap which indicates that the hardware supports a
> pitch with 'byte-granularity'. If the cap is not set, assume that
> we need pitch aligned to cpp.
> 
> We set this cap later for the drivers/planes that support it.
> 
> Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
> ---
>  drivers/gpu/drm/exynos/exynos_drm_drv.h   |  1 +
>  drivers/gpu/drm/exynos/exynos_drm_plane.c | 10 ++++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h
> index 43afab4bebc3..ec32632485d2 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
> +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
> @@ -92,6 +92,7 @@ struct exynos_drm_plane {
>  #define EXYNOS_DRM_PLANE_CAP_SCALE	(1 << 1)
>  #define EXYNOS_DRM_PLANE_CAP_ZPOS	(1 << 2)
>  #define EXYNOS_DRM_PLANE_CAP_TILE	(1 << 3)
> +#define EXYNOS_DRM_PLANE_CAP_BYTE_PITCH	(1 << 4)

I don't see why this flag is required because cpp value is given always. So I think we can check the pitch alignment regardless of a given flag.
BTW, it'd better for pitch alignment to be checked by drm core?

>  
>  /*
>   * Exynos DRM plane configuration structure.
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c
> index bd3825617b06..734d5ba4eb99 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
> @@ -185,6 +185,16 @@ exynos_drm_plane_check_format(const struct exynos_drm_plane_config *config,
>  {
>  	struct drm_framebuffer *fb = state->base.fb;
>  
> +	/*
> +	 * Some blocks only allow to specify a buffer pitch in terms
> +	 * of pixels. In these cases, we need to ensure that the pitch
> +	 * provided by userspace is divisible by the cpp.
> +	 */
> +	if (!(config->capabilities & EXYNOS_DRM_PLANE_CAP_BYTE_PITCH)) {
> +		if (fb->pitches[0] % fb->format->cpp[0])
> +			return -ENOTSUPP;
> +	}
> +
>  	switch (fb->modifier) {
>  	case DRM_FORMAT_MOD_SAMSUNG_64_32_TILE:
>  		if (!(config->capabilities & EXYNOS_DRM_PLANE_CAP_TILE))
>
Tobias Jakobi - Aug. 11, 2017, 11:44 a.m.
Inki Dae wrote:
> 
> 
> 2017년 08월 09일 20:48에 Tobias Jakobi 이(가) 쓴 글:
>> In some of drivers we compute something like 'pitch / cpp' at some
>> point, silently assuming that the pitch (which is in bytes) is
>> divisible by the buffer's cpp. This is not always true, in particular
>> DRM core does not check for pitch alignment in the common case.
>>
>> Introduce a new cap which indicates that the hardware supports a
>> pitch with 'byte-granularity'. If the cap is not set, assume that
>> we need pitch aligned to cpp.
>>
>> We set this cap later for the drivers/planes that support it.
>>
>> Signed-off-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
>> ---
>>  drivers/gpu/drm/exynos/exynos_drm_drv.h   |  1 +
>>  drivers/gpu/drm/exynos/exynos_drm_plane.c | 10 ++++++++++
>>  2 files changed, 11 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h
>> index 43afab4bebc3..ec32632485d2 100644
>> --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
>> +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
>> @@ -92,6 +92,7 @@ struct exynos_drm_plane {
>>  #define EXYNOS_DRM_PLANE_CAP_SCALE	(1 << 1)
>>  #define EXYNOS_DRM_PLANE_CAP_ZPOS	(1 << 2)
>>  #define EXYNOS_DRM_PLANE_CAP_TILE	(1 << 3)
>> +#define EXYNOS_DRM_PLANE_CAP_BYTE_PITCH	(1 << 4)
> 
> I don't see why this flag is required because cpp value is given always. So I think we can check the pitch alignment regardless of a given flag.
> BTW, it'd better for pitch alignment to be checked by drm core?
How do you want to check the pitch value, if you don't know what the HW can handle?

- Tobias

> 
>>  
>>  /*
>>   * Exynos DRM plane configuration structure.
>> diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c
>> index bd3825617b06..734d5ba4eb99 100644
>> --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
>> +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
>> @@ -185,6 +185,16 @@ exynos_drm_plane_check_format(const struct exynos_drm_plane_config *config,
>>  {
>>  	struct drm_framebuffer *fb = state->base.fb;
>>  
>> +	/*
>> +	 * Some blocks only allow to specify a buffer pitch in terms
>> +	 * of pixels. In these cases, we need to ensure that the pitch
>> +	 * provided by userspace is divisible by the cpp.
>> +	 */
>> +	if (!(config->capabilities & EXYNOS_DRM_PLANE_CAP_BYTE_PITCH)) {
>> +		if (fb->pitches[0] % fb->format->cpp[0])
>> +			return -ENOTSUPP;
>> +	}
>> +
>>  	switch (fb->modifier) {
>>  	case DRM_FORMAT_MOD_SAMSUNG_64_32_TILE:
>>  		if (!(config->capabilities & EXYNOS_DRM_PLANE_CAP_TILE))
>>
> --
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Patch

diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index 43afab4bebc3..ec32632485d2 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -92,6 +92,7 @@  struct exynos_drm_plane {
 #define EXYNOS_DRM_PLANE_CAP_SCALE	(1 << 1)
 #define EXYNOS_DRM_PLANE_CAP_ZPOS	(1 << 2)
 #define EXYNOS_DRM_PLANE_CAP_TILE	(1 << 3)
+#define EXYNOS_DRM_PLANE_CAP_BYTE_PITCH	(1 << 4)
 
 /*
  * Exynos DRM plane configuration structure.
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c
index bd3825617b06..734d5ba4eb99 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
@@ -185,6 +185,16 @@  exynos_drm_plane_check_format(const struct exynos_drm_plane_config *config,
 {
 	struct drm_framebuffer *fb = state->base.fb;
 
+	/*
+	 * Some blocks only allow to specify a buffer pitch in terms
+	 * of pixels. In these cases, we need to ensure that the pitch
+	 * provided by userspace is divisible by the cpp.
+	 */
+	if (!(config->capabilities & EXYNOS_DRM_PLANE_CAP_BYTE_PITCH)) {
+		if (fb->pitches[0] % fb->format->cpp[0])
+			return -ENOTSUPP;
+	}
+
 	switch (fb->modifier) {
 	case DRM_FORMAT_MOD_SAMSUNG_64_32_TILE:
 		if (!(config->capabilities & EXYNOS_DRM_PLANE_CAP_TILE))