| Message ID | 1502445086-10063-1-git-send-email-joonas.lahtinen@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Quoting Joonas Lahtinen (2017-08-11 10:51:26) > Configurations like virtualized environments may support only 48 bit > ppGTT without supporting 32 bit ppGTT. Support this by disconnecting > the relationship of the two feature bits. Did the gvt patches land in dinq? After that, I say we just kill the module parameter, and so make the choice of GTT mode much easier to follow. Have we ever asked a user to debug a problem by changing GTT modes in the last 5 years? -Chris
On 2017.08.14 20:34:48 +0800, Zhi Wang wrote: > Looks has_full_48bit_ppgtt is tied to has_full_ppgtt now. Will that be > disconnected also in future? > That's what this is for. So for gvt, we just set has_full_48bit_ppgtt but not has_full_ppgtt. > On 08/11/17 17:51, Joonas Lahtinen wrote: > > Configurations like virtualized environments may support only 48 bit > > ppGTT without supporting 32 bit ppGTT. Support this by disconnecting > > the relationship of the two feature bits. > > > > Cc: Tina Zhang <tina.zhang@intel.com> > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > > Cc: Zhi Wang <zhi.a.wang@intel.com> > > Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > > --- > > drivers/gpu/drm/i915/i915_gem_gtt.c | 13 +++++++++---- > > 1 file changed, 9 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > > index 10aa776..a5eada1 100644 > > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > > @@ -180,10 +180,15 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, > > return 0; > > } > > - if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt) > > - return has_full_48bit_ppgtt ? 3 : 2; > > - else > > - return has_aliasing_ppgtt ? 1 : 0; > > + if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists) { > > + if (has_full_48bit_ppgtt) > > + return 3; > > + > > + if (has_full_ppgtt) > > + return 2; > > + } > > + > > + return has_aliasing_ppgtt ? 1 : 0; > > } > > static int ppgtt_bind_vma(struct i915_vma *vma, > > > --------------------------------------------------------------------- > Intel Finland Oy > Registered Address: PL 281, 00181 Helsinki Business Identity Code: 0357606 - > 4 Domiciled in Helsinki > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Thanks! LGTM. :) -----Original Message----- From: Zhenyu Wang [mailto:zhenyuw@linux.intel.com] Sent: Monday, August 14, 2017 3:01 PM To: Wang, Zhi A <zhi.a.wang@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>; Intel graphics driver community testing & development <intel-gfx@lists.freedesktop.org> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Disconnect 32 and 48 bit ppGTT support On 2017.08.14 20:34:48 +0800, Zhi Wang wrote: > Looks has_full_48bit_ppgtt is tied to has_full_ppgtt now. Will that be > disconnected also in future? > That's what this is for. So for gvt, we just set has_full_48bit_ppgtt but not has_full_ppgtt. > On 08/11/17 17:51, Joonas Lahtinen wrote: > > Configurations like virtualized environments may support only 48 bit > > ppGTT without supporting 32 bit ppGTT. Support this by disconnecting > > the relationship of the two feature bits. > > > > Cc: Tina Zhang <tina.zhang@intel.com> > > Cc: Chris Wilson <chris@chris-wilson.co.uk> > > Cc: Zhi Wang <zhi.a.wang@intel.com> > > Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > > --- > > drivers/gpu/drm/i915/i915_gem_gtt.c | 13 +++++++++---- > > 1 file changed, 9 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c > > b/drivers/gpu/drm/i915/i915_gem_gtt.c > > index 10aa776..a5eada1 100644 > > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > > @@ -180,10 +180,15 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, > > return 0; > > } > > - if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt) > > - return has_full_48bit_ppgtt ? 3 : 2; > > - else > > - return has_aliasing_ppgtt ? 1 : 0; > > + if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists) { > > + if (has_full_48bit_ppgtt) > > + return 3; > > + > > + if (has_full_ppgtt) > > + return 2; > > + } > > + > > + return has_aliasing_ppgtt ? 1 : 0; > > } > > static int ppgtt_bind_vma(struct i915_vma *vma, > > > --------------------------------------------------------------------- > Intel Finland Oy > Registered Address: PL 281, 00181 Helsinki Business Identity Code: > 0357606 - > 4 Domiciled in Helsinki > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Open Source Technology Center, Intel ltd. $gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827 --------------------------------------------------------------------- Intel Finland Oy Registered Address: PL 281, 00181 Helsinki Business Identity Code: 0357606 - 4 Domiciled in Helsinki This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies.
Looks has_full_48bit_ppgtt is tied to has_full_ppgtt now. Will that be disconnected also in future? On 08/11/17 17:51, Joonas Lahtinen wrote: > Configurations like virtualized environments may support only 48 bit > ppGTT without supporting 32 bit ppGTT. Support this by disconnecting > the relationship of the two feature bits. > > Cc: Tina Zhang <tina.zhang@intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Zhi Wang <zhi.a.wang@intel.com> > Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 13 +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 10aa776..a5eada1 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -180,10 +180,15 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, > return 0; > } > > - if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt) > - return has_full_48bit_ppgtt ? 3 : 2; > - else > - return has_aliasing_ppgtt ? 1 : 0; > + if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists) { > + if (has_full_48bit_ppgtt) > + return 3; > + > + if (has_full_ppgtt) > + return 2; > + } > + > + return has_aliasing_ppgtt ? 1 : 0; > } > > static int ppgtt_bind_vma(struct i915_vma *vma, > --------------------------------------------------------------------- Intel Finland Oy Registered Address: PL 281, 00181 Helsinki Business Identity Code: 0357606 - 4 Domiciled in Helsinki This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies.
Glad to see this happen. :) After this patch landed, some code pieces in i915 which are specifically for disabling dynamic PDP update via LRIs under 32 bit PPGTT could also be removed. For example, gen8_preallocate_top_level_pdp() in i915_gem_gtt.c Thanks, Zhi. On 08/11/17 18:30, Chris Wilson wrote: > Quoting Joonas Lahtinen (2017-08-11 10:51:26) >> Configurations like virtualized environments may support only 48 bit >> ppGTT without supporting 32 bit ppGTT. Support this by disconnecting >> the relationship of the two feature bits. > > Did the gvt patches land in dinq? After that, I say we just kill the > module parameter, and so make the choice of GTT mode much easier to follow. > > Have we ever asked a user to debug a problem by changing GTT modes in > the last 5 years? > -Chris >
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 10aa776..a5eada1 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -180,10 +180,15 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, return 0; } - if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists && has_full_ppgtt) - return has_full_48bit_ppgtt ? 3 : 2; - else - return has_aliasing_ppgtt ? 1 : 0; + if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists) { + if (has_full_48bit_ppgtt) + return 3; + + if (has_full_ppgtt) + return 2; + } + + return has_aliasing_ppgtt ? 1 : 0; } static int ppgtt_bind_vma(struct i915_vma *vma,
Configurations like virtualized environments may support only 48 bit ppGTT without supporting 32 bit ppGTT. Support this by disconnecting the relationship of the two feature bits. Cc: Tina Zhang <tina.zhang@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Cc: Zhi Wang <zhi.a.wang@intel.com> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> --- drivers/gpu/drm/i915/i915_gem_gtt.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-)