[v6,1/5] drm/vc4: Move the DSI clock divider workaround closer to the clock call.
diff mbox

Message ID 20170815234722.20700-1-eric@anholt.net
State New
Headers show

Commit Message

Eric Anholt Aug. 15, 2017, 11:47 p.m. UTC
We want the adjusted_mode->clock to be the actual clock we're
expecting to program, so that consumers see the right values for clock
and vrefresh.

Signed-off-by: Eric Anholt <eric@anholt.net>
---
 drivers/gpu/drm/vc4/vc4_dsi.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Comments

Boris BREZILLON Oct. 11, 2017, 11:54 a.m. UTC | #1
On Tue, 15 Aug 2017 16:47:18 -0700
Eric Anholt <eric@anholt.net> wrote:

> We want the adjusted_mode->clock to be the actual clock we're
> expecting to program, so that consumers see the right values for clock
> and vrefresh.
> 
> Signed-off-by: Eric Anholt <eric@anholt.net>

Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>

> ---
>  drivers/gpu/drm/vc4/vc4_dsi.c | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c
> index d1e0dc908048..eb787eed8abe 100644
> --- a/drivers/gpu/drm/vc4/vc4_dsi.c
> +++ b/drivers/gpu/drm/vc4/vc4_dsi.c
> @@ -859,11 +859,7 @@ static bool vc4_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
>  	pll_clock = parent_rate / divider;
>  	pixel_clock_hz = pll_clock / dsi->divider;
>  
> -	/* Round up the clk_set_rate() request slightly, since
> -	 * PLLD_DSI1 is an integer divider and its rate selection will
> -	 * never round up.
> -	 */
> -	adjusted_mode->clock = pixel_clock_hz / 1000 + 1;
> +	adjusted_mode->clock = pixel_clock_hz / 1000;
>  
>  	/* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
>  	adjusted_mode->htotal = pixel_clock_hz / (mode->vrefresh * mode->vtotal);
> @@ -900,7 +896,11 @@ static void vc4_dsi_encoder_enable(struct drm_encoder *encoder)
>  		vc4_dsi_dump_regs(dsi);
>  	}
>  
> -	phy_clock = pixel_clock_hz * dsi->divider;
> +	/* Round up the clk_set_rate() request slightly, since
> +	 * PLLD_DSI1 is an integer divider and its rate selection will
> +	 * never round up.
> +	 */
> +	phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
>  	ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
>  	if (ret) {
>  		dev_err(&dsi->pdev->dev,

Patch
diff mbox

diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c
index d1e0dc908048..eb787eed8abe 100644
--- a/drivers/gpu/drm/vc4/vc4_dsi.c
+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
@@ -859,11 +859,7 @@  static bool vc4_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
 	pll_clock = parent_rate / divider;
 	pixel_clock_hz = pll_clock / dsi->divider;
 
-	/* Round up the clk_set_rate() request slightly, since
-	 * PLLD_DSI1 is an integer divider and its rate selection will
-	 * never round up.
-	 */
-	adjusted_mode->clock = pixel_clock_hz / 1000 + 1;
+	adjusted_mode->clock = pixel_clock_hz / 1000;
 
 	/* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
 	adjusted_mode->htotal = pixel_clock_hz / (mode->vrefresh * mode->vtotal);
@@ -900,7 +896,11 @@  static void vc4_dsi_encoder_enable(struct drm_encoder *encoder)
 		vc4_dsi_dump_regs(dsi);
 	}
 
-	phy_clock = pixel_clock_hz * dsi->divider;
+	/* Round up the clk_set_rate() request slightly, since
+	 * PLLD_DSI1 is an integer divider and its rate selection will
+	 * never round up.
+	 */
+	phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
 	ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
 	if (ret) {
 		dev_err(&dsi->pdev->dev,