| Message ID | 1503303367-17915-5-git-send-email-zhangqing@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi Elaine, 在 2017/8/21 16:16, Elaine Zhang 写道: > cru_sel24_con[8] > rmii_extclk_sel > clock source select control register > 1'b0: from internal PLL > 1'b1: from external IO > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> > --- > drivers/clk/rockchip/clk-rv1108.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/rockchip/clk-rv1108.c b/drivers/clk/rockchip/clk-rv1108.c > index 658da17c9d99..4d87828df4f7 100644 > --- a/drivers/clk/rockchip/clk-rv1108.c > +++ b/drivers/clk/rockchip/clk-rv1108.c > @@ -140,7 +140,7 @@ enum rv1108_plls { > PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; > PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; > PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; > -PNAME(mux_sclk_mac_p) = { "ext_gmac", "sclk_mac_pre" }; > +PNAME(mux_sclk_mac_p) = { "sclk_mac_pre", "ext_gmac" }; > PNAME(mux_i2s0_pre_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; > PNAME(mux_i2s_out_p) = { "i2s0_pre", "xin12m" }; > PNAME(mux_i2s1_p) = { "i2s1_src", "i2s1_frac", "dummy", "xin12m" }; > Acked-by: David Wu <david.wu@rock-chips.com>
Am Montag, 21. August 2017, 16:16:07 CEST schrieb Elaine Zhang: > cru_sel24_con[8] > rmii_extclk_sel > clock source select control register > 1'b0: from internal PLL > 1'b1: from external IO > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> applied for 4.14. Thanks Heiko
diff --git a/drivers/clk/rockchip/clk-rv1108.c b/drivers/clk/rockchip/clk-rv1108.c index 658da17c9d99..4d87828df4f7 100644 --- a/drivers/clk/rockchip/clk-rv1108.c +++ b/drivers/clk/rockchip/clk-rv1108.c @@ -140,7 +140,7 @@ enum rv1108_plls { PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" }; PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" }; PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" }; -PNAME(mux_sclk_mac_p) = { "ext_gmac", "sclk_mac_pre" }; +PNAME(mux_sclk_mac_p) = { "sclk_mac_pre", "ext_gmac" }; PNAME(mux_i2s0_pre_p) = { "i2s0_src", "i2s0_frac", "ext_i2s", "xin12m" }; PNAME(mux_i2s_out_p) = { "i2s0_pre", "xin12m" }; PNAME(mux_i2s1_p) = { "i2s1_src", "i2s1_frac", "dummy", "xin12m" };
cru_sel24_con[8] rmii_extclk_sel clock source select control register 1'b0: from internal PLL 1'b1: from external IO Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> --- drivers/clk/rockchip/clk-rv1108.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)