From patchwork Fri Sep 1 17:30:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jarkko Sakkinen X-Patchwork-Id: 9934971 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0F413603B4 for ; Fri, 1 Sep 2017 17:30:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EAE1127F2B for ; Fri, 1 Sep 2017 17:30:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E971A28173; Fri, 1 Sep 2017 17:30:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from ml01.01.org (ml01.01.org [198.145.21.10]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9306F28382 for ; Fri, 1 Sep 2017 17:30:47 +0000 (UTC) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C352721E62BA7; Fri, 1 Sep 2017 10:28:02 -0700 (PDT) X-Original-To: intel-sgx-kernel-dev@lists.01.org Delivered-To: intel-sgx-kernel-dev@lists.01.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A478A21E62BB1 for ; Fri, 1 Sep 2017 10:28:00 -0700 (PDT) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Sep 2017 10:30:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,459,1498546800"; d="scan'208";a="146559050" Received: from jsakkine-mobl1.tm.intel.com (HELO localhost) ([10.237.50.92]) by fmsmga005.fm.intel.com with ESMTP; 01 Sep 2017 10:30:31 -0700 From: Jarkko Sakkinen To: intel-sgx-kernel-dev@lists.01.org Date: Fri, 1 Sep 2017 20:30:02 +0300 Message-Id: <20170901173002.8442-11-jarkko.sakkinen@linux.intel.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170901173002.8442-1-jarkko.sakkinen@linux.intel.com> References: <20170901173002.8442-1-jarkko.sakkinen@linux.intel.com> Subject: [intel-sgx-kernel-dev] [PATCH RFC 10/10] intel_sgx: update IA32_SGXLEPUBKEYHASH* MSRs X-BeenThere: intel-sgx-kernel-dev@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: "Project: Intel® Software Guard Extensions for Linux*: https://01.org/intel-software-guard-extensions" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-sgx-kernel-dev-bounces@lists.01.org Sender: "intel-sgx-kernel-dev" X-Virus-Scanned: ClamAV using ClamSMTP Check if IA32_SGXLEPUBKEYHASH* MSRs match. If they do not match, allow the driver initialization to continue only if they are writable. In this case update them with the MRSIGNER of the launch enclave. Signed-off-by: Jarkko Sakkinen --- drivers/platform/x86/intel_sgx/sgx.h | 3 ++ drivers/platform/x86/intel_sgx/sgx_encl.c | 45 ++++++++++++++++++++++ .../platform/x86/intel_sgx/sgx_le_proxy_piggy.S | 4 ++ drivers/platform/x86/intel_sgx/sgx_main.c | 26 +++++++++++++ 4 files changed, 78 insertions(+) diff --git a/drivers/platform/x86/intel_sgx/sgx.h b/drivers/platform/x86/intel_sgx/sgx.h index 338a8bf7acfd..2399871d2e0b 100644 --- a/drivers/platform/x86/intel_sgx/sgx.h +++ b/drivers/platform/x86/intel_sgx/sgx.h @@ -164,6 +164,9 @@ extern u64 sgx_encl_size_max_64; extern u64 sgx_xfrm_mask; extern u32 sgx_ssaframesize_tbl[64]; extern bool sgx_has_sgx2; +extern bool sgx_locked_msrs; +extern void *sgx_msrs_set; +extern u64 sgx_le_pubkeyhash[4]; extern const struct file_operations sgx_fops; extern const struct vm_operations_struct sgx_vm_ops; diff --git a/drivers/platform/x86/intel_sgx/sgx_encl.c b/drivers/platform/x86/intel_sgx/sgx_encl.c index cde732bb6e83..3167dbb0452f 100644 --- a/drivers/platform/x86/intel_sgx/sgx_encl.c +++ b/drivers/platform/x86/intel_sgx/sgx_encl.c @@ -68,6 +68,7 @@ #include #include #include +#include struct sgx_add_page_req { struct sgx_encl *encl; @@ -732,12 +733,47 @@ int sgx_encl_add_page(struct sgx_encl *encl, unsigned long addr, void *data, return ret; } +static void *sgx_set_pubkeyhash_msrs(void) +{ + u64 msrs_pubkeyhash[4]; + bool *msrs_set; + + msrs_set = get_cpu_var(sgx_msrs_set); + if (*msrs_set) + return msrs_set; + + rdmsrl(MSR_IA32_SGXLEPUBKEYHASH0, msrs_pubkeyhash[0]); + rdmsrl(MSR_IA32_SGXLEPUBKEYHASH1, msrs_pubkeyhash[1]); + rdmsrl(MSR_IA32_SGXLEPUBKEYHASH2, msrs_pubkeyhash[2]); + rdmsrl(MSR_IA32_SGXLEPUBKEYHASH3, msrs_pubkeyhash[3]); + + if ((sgx_le_pubkeyhash[0] == msrs_pubkeyhash[0]) && + (sgx_le_pubkeyhash[1] == msrs_pubkeyhash[1]) && + (sgx_le_pubkeyhash[2] == msrs_pubkeyhash[2]) && + (sgx_le_pubkeyhash[3] == msrs_pubkeyhash[3])) + return msrs_set; + + if (sgx_locked_msrs) { + pr_err("intel_sgx: the LE public key MSRs do not match\n"); + put_cpu_var(msrs_set); + return ERR_PTR(-ENODEV); + } + + pr_info("intel_sgx: updating the LE public key MSRs\n"); + wrmsrl(MSR_IA32_SGXLEPUBKEYHASH0, sgx_le_pubkeyhash[0]); + wrmsrl(MSR_IA32_SGXLEPUBKEYHASH1, sgx_le_pubkeyhash[1]); + wrmsrl(MSR_IA32_SGXLEPUBKEYHASH2, sgx_le_pubkeyhash[2]); + wrmsrl(MSR_IA32_SGXLEPUBKEYHASH3, sgx_le_pubkeyhash[3]); + return msrs_set; +} + int sgx_encl_init(struct sgx_encl *encl, struct sgx_sigstruct *sigstruct, struct sgx_einittoken *einittoken) { int ret = SGX_UNMASKED_EVENT; struct sgx_epc_page *secs_epc = encl->secs_page.epc_page; void *secs_va = NULL; + void *cpu_lock; int i; int j; @@ -752,9 +788,18 @@ int sgx_encl_init(struct sgx_encl *encl, struct sgx_sigstruct *sigstruct, for (i = 0; i < SGX_EINIT_SLEEP_COUNT; i++) { for (j = 0; j < SGX_EINIT_SPIN_COUNT; j++) { + cpu_lock = sgx_set_pubkeyhash_msrs(); + if (IS_ERR(cpu_lock)) { + mutex_unlock(&encl->lock); + return PTR_ERR(cpu_lock); + } + secs_va = sgx_get_page(secs_epc); ret = __einit(sigstruct, einittoken, secs_va); sgx_put_page(secs_va); + + put_cpu_var(cpu_lock); + if (ret == SGX_UNMASKED_EVENT) continue; else diff --git a/drivers/platform/x86/intel_sgx/sgx_le_proxy_piggy.S b/drivers/platform/x86/intel_sgx/sgx_le_proxy_piggy.S index faced8a9a75a..e1e3742a0c93 100644 --- a/drivers/platform/x86/intel_sgx/sgx_le_proxy_piggy.S +++ b/drivers/platform/x86/intel_sgx/sgx_le_proxy_piggy.S @@ -9,3 +9,7 @@ GLOBAL(sgx_le_proxy) END(sgx_le_proxy) GLOBAL(sgx_le_proxy_end) + +GLOBAL(sgx_le_ss) + .incbin "drivers/platform/x86/intel_sgx/le/enclave/sgx_le.ss" +END(sgx_le_ss) diff --git a/drivers/platform/x86/intel_sgx/sgx_main.c b/drivers/platform/x86/intel_sgx/sgx_main.c index baebc233b3e9..e4364d4d77bb 100644 --- a/drivers/platform/x86/intel_sgx/sgx_main.c +++ b/drivers/platform/x86/intel_sgx/sgx_main.c @@ -68,6 +68,7 @@ #include #include #include +#include #define DRV_DESCRIPTION "Intel SGX Driver" #define DRV_VERSION "0.10" @@ -80,6 +81,7 @@ MODULE_VERSION(DRV_VERSION); * Global data. */ +extern struct sgx_sigstruct sgx_le_ss; struct workqueue_struct *sgx_add_page_wq; #define SGX_MAX_EPC_BANKS 8 struct sgx_epc_bank sgx_epc_banks[SGX_MAX_EPC_BANKS]; @@ -89,6 +91,9 @@ u64 sgx_encl_size_max_64; u64 sgx_xfrm_mask = 0x3; u32 sgx_ssaframesize_tbl[64]; bool sgx_has_sgx2; +bool sgx_locked_msrs; +void *sgx_msrs_set; +u64 sgx_le_pubkeyhash[4]; #ifdef CONFIG_COMPAT long sgx_compat_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) @@ -191,6 +196,14 @@ static int sgx_dev_init(struct device *dev) if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) return -ENODEV; + sgx_msrs_set = alloc_percpu(bool); + if (!sgx_msrs_set) + return -ENOMEM; + + ret = sgx_get_key_hash_simple(sgx_le_ss.modulus, sgx_le_pubkeyhash); + if (ret) + return ret; + for (i = 0; i < SGX_MAX_EPC_BANKS; i++) { cpuid_count(SGX_CPUID, i + 2, &eax, &ebx, &ecx, &edx); if (!(eax & 0xf)) @@ -268,6 +281,7 @@ static int sgx_dev_init(struct device *dev) static int sgx_drv_probe(struct platform_device *pdev) { unsigned int eax, ebx, ecx, edx; + unsigned long fc; int i; if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) @@ -284,6 +298,17 @@ static int sgx_drv_probe(struct platform_device *pdev) return -ENODEV; } + if (!boot_cpu_has(X86_FEATURE_SGX_LC)) { + pr_err("intel_sgx: the CPU is missing launch control\n"); + return -ENODEV; + } + + rdmsrl(MSR_IA32_FEATURE_CONTROL, fc); + if (!(fc & FEATURE_CONTROL_SGX_LAUNCH_CONTROL_ENABLE)) { + pr_info("intel_sgx: the LE public key MSRs are locked\n"); + sgx_locked_msrs = true; + } + cpuid_count(SGX_CPUID, 0x0, &eax, &ebx, &ecx, &edx); if (!(eax & 1)) { pr_err("intel_sgx: CPU does not support the SGX1 instructions\n"); @@ -328,6 +353,7 @@ static int sgx_drv_remove(struct platform_device *pdev) iounmap((void *)sgx_epc_banks[i].va); #endif sgx_page_cache_teardown(); + free_percpu(sgx_msrs_set); return 0; }