From patchwork Sun Sep 3 12:07:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 9936119 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9A36F6037D for ; Sun, 3 Sep 2017 12:09:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8B9F92866E for ; Sun, 3 Sep 2017 12:09:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 80387286B0; Sun, 3 Sep 2017 12:09:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from mother.openwall.net (mother.openwall.net [195.42.179.200]) by mail.wl.linuxfoundation.org (Postfix) with SMTP id 8E73D2866E for ; Sun, 3 Sep 2017 12:09:30 +0000 (UTC) Received: (qmail 9821 invoked by uid 550); 3 Sep 2017 12:08:48 -0000 Mailing-List: contact kernel-hardening-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Delivered-To: mailing list kernel-hardening@lists.openwall.com Received: (qmail 9711 invoked from network); 3 Sep 2017 12:08:47 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=zlboNm/Dz+QHErR9YXIMWDbt/5JEH8elUkiSpKHh3+U=; b=NbomJ1FYAVUzA6Ru9tFakg8Fm915alr1q78zYamlvwDc4RCkuTRRi0AQXzFduE1ybc sdauvXev6SRoBXWTM/CmD6zqS2IJQpyyww0/8kubvKlfb0rROck99IGSu31ad2z0SOOG UkPvb21kQpYahpUYjGZQotaHRVDFOKGFFvkds= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=zlboNm/Dz+QHErR9YXIMWDbt/5JEH8elUkiSpKHh3+U=; b=aAaqZWDNIxIQ12KRHj0tC0xXzmdCl7B/BmIm5mAGDrInNiGgyJUxHXWb3Uj0o+4TpS NqKzMHhsQmxHaqE72CsBsTwUEEYDjScyc7/iidm67l4pZnONNU3J61dLNBkmZWgrK8zj AvuGoHC03sapIIdVdTfcL39z+8+kL10J94eupHUlcaGsfTrBNq/9nyFFjhiZ2Pb4au5U O3UaG3kX/XxoHyJca+QAECMkXI5L2LnHiih0eNd55oGRtrIi97N8VK6K/Bk9tj9snZy8 +3AvSGXg3DDyLUknmdCce0TMzEvRMiJfAbBBajt8gymeBDVyJ6qpY37nTaXxlrc81+rZ ZICA== X-Gm-Message-State: AHPjjUgkeWm6WNaUDoj4hEd24f4kpfOomjzSwNxjxpzNn/G99ACxv7I6 hLHzPXvnYBx3z/CH X-Google-Smtp-Source: ADKCNb6g7oF6Kf7+FptfWUvrkBEMK1G/AIXCoL7GMV71sNDx1LMPXSIWOSEdwgZEGt06p+F7UxYIXA== X-Received: by 10.28.109.220 with SMTP id b89mr2626588wmi.106.1504440515721; Sun, 03 Sep 2017 05:08:35 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org, kernel-hardening@lists.openwall.com Cc: Ard Biesheuvel , Arnd Bergmann , Nicolas Pitre , Russell King , Kees Cook , Thomas Garnier , Marc Zyngier , Mark Rutland , Tony Lindgren , Matt Fleming , Dave Martin Date: Sun, 3 Sep 2017 13:07:34 +0100 Message-Id: <20170903120757.14968-7-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170903120757.14968-1-ard.biesheuvel@linaro.org> References: <20170903120757.14968-1-ard.biesheuvel@linaro.org> Subject: [kernel-hardening] [PATCH v2 06/29] ARM: head.S: use PC-relative insn sequence for secondary_data X-Virus-Scanned: ClamAV using ClamSMTP Replace the open coded PC relative offset calculations with adr_l and ldr_l invocations. This ensures these quantities are invariant under runtime relocation. Cc: Russell King Signed-off-by: Ard Biesheuvel Acked-by: Nicolas Pitre --- arch/arm/kernel/head.S | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 0a98aec0e39d..6e9df3663a57 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -386,10 +386,8 @@ ENTRY(secondary_startup) /* * Use the page tables supplied from __cpu_up. */ - adr r4, __secondary_data - ldmia r4, {r5, r7, r12} @ address to jump to after - sub lr, r4, r5 @ mmu has been enabled - add r3, r7, lr + adr_l r3, secondary_data + mov_l r12, __secondary_switched ldrd r4, [r3, #0] @ get secondary_data.pgdir ARM_BE8(eor r4, r4, r5) @ Swap r5 and r4 in BE: ARM_BE8(eor r5, r4, r5) @ it can be done in 3 steps @@ -404,22 +402,13 @@ ARM_BE8(eor r4, r4, r5) @ without using a temp reg. ENDPROC(secondary_startup) ENDPROC(secondary_startup_arm) - /* - * r6 = &secondary_data - */ ENTRY(__secondary_switched) - ldr sp, [r7, #12] @ get secondary_data.stack + ldr_l r7, secondary_data + 12 @ get secondary_data.stack + mov sp, r7 mov fp, #0 b secondary_start_kernel ENDPROC(__secondary_switched) - .align - - .type __secondary_data, %object -__secondary_data: - .long . - .long secondary_data - .long __secondary_switched #endif /* defined(CONFIG_SMP) */