[2/2] drm/i915/huc: Add HuC Load time to debugfs
diff mbox

Message ID 20170907003740.3016-2-anusha.srivatsa@intel.com
State New
Headers show

Commit Message

Srivatsa, Anusha Sept. 7, 2017, 12:37 a.m. UTC
This patch uses jiffies to calculate the huc
load time and add it as a field to debugfs.
This information can be useful for testing
to know how much time huc takes to load.

Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com>
Cc: Oscar Mateo Lozano <oscar.mateo.lozano@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
 drivers/gpu/drm/i915/intel_huc.c    | 8 ++++++++
 drivers/gpu/drm/i915/intel_uc.h     | 1 +
 3 files changed, 11 insertions(+)

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e0b99dbc6608..a8a8a210a97c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2349,6 +2349,8 @@  static int i915_huc_load_status_info(struct seq_file *m, void *data)
 		huc_fw->header_offset, huc_fw->header_size);
 	seq_printf(m, "\tuCode: offset is %d; size = %d\n",
 		huc_fw->ucode_offset, huc_fw->ucode_size);
+	seq_printf(m, "\tHuC load time is %lu ms\n",
+		   jiffies_to_msecs(huc_fw->huc_load_time));
 	seq_printf(m, "\tRSA: offset is %d; size = %d\n",
 		huc_fw->rsa_offset, huc_fw->rsa_size);
 
diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c
index 6145fa0d6773..798dec9bd2c8 100644
--- a/drivers/gpu/drm/i915/intel_huc.c
+++ b/drivers/gpu/drm/i915/intel_huc.c
@@ -90,6 +90,7 @@  static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
 	unsigned long offset = 0;
 	u32 size;
 	int ret;
+	unsigned long huc_start_load, huc_finish_load;
 
 	ret = i915_gem_object_set_to_gtt_domain(huc_fw->obj, false);
 	if (ret) {
@@ -121,11 +122,15 @@  static int huc_ucode_xfer(struct drm_i915_private *dev_priv)
 	I915_WRITE(DMA_COPY_SIZE, size);
 
 	/* Start the DMA */
+	huc_start_load = jiffies;
 	I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA));
 
 	/* Wait for DMA to finish */
 	ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100);
 
+	huc_finish_load = jiffies;
+	huc_fw->huc_load_time = huc_finish_load - huc_start_load;
+
 	DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret);
 
 	/* Disable the bits once DMA is over */
@@ -218,6 +223,9 @@  void intel_huc_init_hw(struct intel_huc *huc)
 		intel_uc_fw_status_repr(huc->fw.fetch_status),
 		intel_uc_fw_status_repr(huc->fw.load_status));
 
+	DRM_DEBUG_DRIVER("Time taken to load HuC %lu",
+			 huc->fw.huc_load_time);
+
 	if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
 		DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err);
 
diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h
index 52aa05d13863..1ef685d7095e 100644
--- a/drivers/gpu/drm/i915/intel_uc.h
+++ b/drivers/gpu/drm/i915/intel_uc.h
@@ -155,6 +155,7 @@  struct intel_uc_fw {
 	uint32_t ucode_size;
 	uint32_t ucode_offset;
 	unsigned long guc_load_time;
+	unsigned long huc_load_time;
 };
 
 struct intel_guc_log {