From patchwork Thu Sep 7 00:37:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Srivatsa, Anusha" X-Patchwork-Id: 9941523 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 306FE6038C for ; Thu, 7 Sep 2017 00:36:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2574126E97 for ; Thu, 7 Sep 2017 00:36:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 199EF274D1; Thu, 7 Sep 2017 00:36:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9FA9D26E97 for ; Thu, 7 Sep 2017 00:36:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AF1D86E76D; Thu, 7 Sep 2017 00:36:10 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id B13926E76E for ; Thu, 7 Sep 2017 00:36:09 +0000 (UTC) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Sep 2017 17:36:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,355,1500966000"; d="scan'208";a="132585900" Received: from anusha-test.jf.intel.com ([10.7.198.157]) by orsmga002.jf.intel.com with ESMTP; 06 Sep 2017 17:36:09 -0700 From: Anusha Srivatsa To: intel-gfx@lists.freedesktop.org Date: Wed, 6 Sep 2017 17:37:40 -0700 Message-Id: <20170907003740.3016-2-anusha.srivatsa@intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170907003740.3016-1-anusha.srivatsa@intel.com> References: <20170907003740.3016-1-anusha.srivatsa@intel.com> Cc: Sujaritha Sundaresan , Oscar Mateo Lozano Subject: [Intel-gfx] [PATCH 2/2] drm/i915/huc: Add HuC Load time to debugfs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This patch uses jiffies to calculate the huc load time and add it as a field to debugfs. This information can be useful for testing to know how much time huc takes to load. Cc: Sujaritha Sundaresan Cc: Oscar Mateo Lozano Cc: Michal Wajdeczko Signed-off-by: Anusha Srivatsa --- drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ drivers/gpu/drm/i915/intel_huc.c | 8 ++++++++ drivers/gpu/drm/i915/intel_uc.h | 1 + 3 files changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index e0b99dbc6608..a8a8a210a97c 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2349,6 +2349,8 @@ static int i915_huc_load_status_info(struct seq_file *m, void *data) huc_fw->header_offset, huc_fw->header_size); seq_printf(m, "\tuCode: offset is %d; size = %d\n", huc_fw->ucode_offset, huc_fw->ucode_size); + seq_printf(m, "\tHuC load time is %lu ms\n", + jiffies_to_msecs(huc_fw->huc_load_time)); seq_printf(m, "\tRSA: offset is %d; size = %d\n", huc_fw->rsa_offset, huc_fw->rsa_size); diff --git a/drivers/gpu/drm/i915/intel_huc.c b/drivers/gpu/drm/i915/intel_huc.c index 6145fa0d6773..798dec9bd2c8 100644 --- a/drivers/gpu/drm/i915/intel_huc.c +++ b/drivers/gpu/drm/i915/intel_huc.c @@ -90,6 +90,7 @@ static int huc_ucode_xfer(struct drm_i915_private *dev_priv) unsigned long offset = 0; u32 size; int ret; + unsigned long huc_start_load, huc_finish_load; ret = i915_gem_object_set_to_gtt_domain(huc_fw->obj, false); if (ret) { @@ -121,11 +122,15 @@ static int huc_ucode_xfer(struct drm_i915_private *dev_priv) I915_WRITE(DMA_COPY_SIZE, size); /* Start the DMA */ + huc_start_load = jiffies; I915_WRITE(DMA_CTRL, _MASKED_BIT_ENABLE(HUC_UKERNEL | START_DMA)); /* Wait for DMA to finish */ ret = wait_for((I915_READ(DMA_CTRL) & START_DMA) == 0, 100); + huc_finish_load = jiffies; + huc_fw->huc_load_time = huc_finish_load - huc_start_load; + DRM_DEBUG_DRIVER("HuC DMA transfer wait over with ret %d\n", ret); /* Disable the bits once DMA is over */ @@ -218,6 +223,9 @@ void intel_huc_init_hw(struct intel_huc *huc) intel_uc_fw_status_repr(huc->fw.fetch_status), intel_uc_fw_status_repr(huc->fw.load_status)); + DRM_DEBUG_DRIVER("Time taken to load HuC %lu", + huc->fw.huc_load_time); + if (huc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) DRM_ERROR("Failed to complete HuC uCode load with ret %d\n", err); diff --git a/drivers/gpu/drm/i915/intel_uc.h b/drivers/gpu/drm/i915/intel_uc.h index 52aa05d13863..1ef685d7095e 100644 --- a/drivers/gpu/drm/i915/intel_uc.h +++ b/drivers/gpu/drm/i915/intel_uc.h @@ -155,6 +155,7 @@ struct intel_uc_fw { uint32_t ucode_size; uint32_t ucode_offset; unsigned long guc_load_time; + unsigned long huc_load_time; }; struct intel_guc_log {