| Message ID | 20170918182604.9519-2-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Quoting Ville Syrjala (2017-09-18 19:25:36) > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Some comments in intel_ddi.c are indented with spaces instead of tabs. > Fix that up. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
On Mon, 18 Sep 2017, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Some comments in intel_ddi.c are indented with spaces instead of tabs. > Fix that up. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/intel_ddi.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index 31d14587ad86..797008033089 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1939,7 +1939,7 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv, > val |= RCOMP_SCALAR(0x98); > I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val); > > - /* Program PORT_TX_DW4 */ > + /* Program PORT_TX_DW4 */ > /* We cannot write to GRP. It would overrite individual loadgen */ > for (ln = 0; ln < 4; ln++) { > val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln)); > @@ -1951,7 +1951,7 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv, > I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val); > } > > - /* Program PORT_TX_DW5 */ > + /* Program PORT_TX_DW5 */ > /* All DW5 values are fixed for every table entry */ > val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); > val &= ~RTERM_SELECT_MASK; > @@ -1959,7 +1959,7 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv, > val |= TAP3_DISABLE; > I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); > > - /* Program PORT_TX_DW7 */ > + /* Program PORT_TX_DW7 */ > val = I915_READ(CNL_PORT_TX_DW7_LN0(port)); > val &= ~N_SCALAR_MASK; > val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 31d14587ad86..797008033089 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1939,7 +1939,7 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv, val |= RCOMP_SCALAR(0x98); I915_WRITE(CNL_PORT_TX_DW2_GRP(port), val); - /* Program PORT_TX_DW4 */ + /* Program PORT_TX_DW4 */ /* We cannot write to GRP. It would overrite individual loadgen */ for (ln = 0; ln < 4; ln++) { val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln)); @@ -1951,7 +1951,7 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv, I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val); } - /* Program PORT_TX_DW5 */ + /* Program PORT_TX_DW5 */ /* All DW5 values are fixed for every table entry */ val = I915_READ(CNL_PORT_TX_DW5_LN0(port)); val &= ~RTERM_SELECT_MASK; @@ -1959,7 +1959,7 @@ static void cnl_ddi_vswing_program(struct drm_i915_private *dev_priv, val |= TAP3_DISABLE; I915_WRITE(CNL_PORT_TX_DW5_GRP(port), val); - /* Program PORT_TX_DW7 */ + /* Program PORT_TX_DW7 */ val = I915_READ(CNL_PORT_TX_DW7_LN0(port)); val &= ~N_SCALAR_MASK; val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);