| Message ID | 20231125092137.2948-1-amit.kumar-mahapatra@amd.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | spi: Add support for stacked/parallel memories | expand |
On Sat, 25 Nov 2023 14:51:27 +0530, Amit Kumar Mahapatra wrote: > This patch series updated the spi-nor, spi core and the AMD-Xilinx GQSPI > driver to add stacked and parallel memories support. > > The first nine patches > https://lore.kernel.org/all/20230119185342.2093323-1-amit.kumar-mahapatra@amd.com/ > https://lore.kernel.org/all/20230310173217.3429788-2-amit.kumar-mahapatra@amd.com/ > https://lore.kernel.org/all/20230310173217.3429788-3-amit.kumar-mahapatra@amd.com/ > https://lore.kernel.org/all/20230310173217.3429788-4-amit.kumar-mahapatra@amd.com/ > https://lore.kernel.org/all/20230310173217.3429788-5-amit.kumar-mahapatra@amd.com/ > https://lore.kernel.org/all/20230310173217.3429788-6-amit.kumar-mahapatra@amd.com/ > https://lore.kernel.org/all/20230310173217.3429788-7-amit.kumar-mahapatra@amd.com/ > https://lore.kernel.org/all/20230310173217.3429788-8-amit.kumar-mahapatra@amd.com/ > https://lore.kernel.org/all/20230310173217.3429788-9-amit.kumar-mahapatra@amd.com/ > of the previous series got applied to > https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git > for-next But the rest of the patches in the series did not get applied as > failure was reported for spi driver with GPIO CS, so send the remaining > patches in the series after rebasing it on top of for-next branch and > fixing the issue. > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next Thanks! [02/10] ALSA: hda/cs35l56: Use set/get APIs to access spi->chip_select commit: f05e2f61fe88092e0d341ea27644a84e3386358d [03/10] spi: Add multi-cs memories support in SPI core commit: 4d8ff6b0991d5e86b17b235fc46ec62e9195cb9b All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark
> This patch series updated the spi-nor, spi core and the AMD-Xilinx > GQSPI > driver to add stacked and parallel memories support. Honestly, I'm not thrilled about how this is implemented in the core and what the restrictions are. First, the pattern "if (n==1) then { old behavior } else { copy old code modify for n==2 }" is hard to maintain. There should be no copy and the old code shall be adapted to work for both n=1 and n>1. But I agree with Tudor, some kind of abstraction (layer) would be nice. Also, you hardcode n=2 everywhere. Please generalize that one. Are you aware of any other controller supporting such a feature? I've seen you also need to modify the spi controller and intercept some commands. Can everything be moved there? I'm not sure we are implementing controller specific things in the core. Hard to judge without seeing other controllers doing a similar thing. I'd like to avoid that. If we had some kind of abstraction here, that might be easier to adapt in the future, but just putting everything into the core will make it really hard to maintain. So if everything related to stacked and parallel memory would be in drivers/mtd/spi-nor/stacked.c, we'd have at least everything in one place with a proper interface between that and the core. -michael
Hello Michael, > -----Original Message----- > From: Michael Walle <michael@walle.cc> > Sent: Tuesday, December 12, 2023 6:05 PM > To: Mahapatra, Amit Kumar <amit.kumar-mahapatra@amd.com> > Cc: broonie@kernel.org; tudor.ambarus@linaro.org; pratyush@kernel.org; > miquel.raynal@bootlin.com; richard@nod.at; vigneshr@ti.com; > sbinding@opensource.cirrus.com; lee@kernel.org; > james.schulman@cirrus.com; david.rhodes@cirrus.com; > rf@opensource.cirrus.com; perex@perex.cz; tiwai@suse.com; linux- > spi@vger.kernel.org; linux-kernel@vger.kernel.org; linux- > mtd@lists.infradead.org; nicolas.ferre@microchip.com; > alexandre.belloni@bootlin.com; claudiu.beznea@tuxon.dev; Simek, Michal > <michal.simek@amd.com>; linux-arm-kernel@lists.infradead.org; alsa- > devel@alsa-project.org; patches@opensource.cirrus.com; linux- > sound@vger.kernel.org; git (AMD-Xilinx) <git@amd.com>; > amitrkcian2002@gmail.com > Subject: Re: [PATCH v11 00/10] spi: Add support for stacked/parallel > memories > > > This patch series updated the spi-nor, spi core and the AMD-Xilinx > > GQSPI driver to add stacked and parallel memories support. > > Honestly, I'm not thrilled about how this is implemented in the core and what > the restrictions are. > First, the pattern "if (n==1) then { old behavior } else { copy old code modify > for n==2 }" is hard to maintain. There should be no copy and the old code > shall be adapted to work for both n=1 and n>1. Stacked mode serves as an extension of single device mode concerning data handling and CS line assertion. In both scenarios, the driver only asserts one CS line at any given time. The existing code has been expanded to determine the CS line to be asserted based on the requested address and data length. This modification accommodates both single (legacy) and stacked use cases. In contrast, parallel mode differs from the legacy (single) mode in terms of data handling. In parallel mode, each byte of data is stored in both devices, with even bits in the lower flash and odd bits in the upper flash. During the transfer, multiple CS lines need to be asserted simultaneously. Consequently, special handling is necessary for parallel mode. > > But I agree with Tudor, some kind of abstraction (layer) would be nice. I agree too. > > Also, you hardcode n=2 everywhere. Please generalize that one. > > Are you aware of any other controller supporting such a feature? I've seen Currently, I am familiar only with the AMD-Xilinx QSPI controllers that support parallel/stacked configurations and AMD-Xilinx OSPI controllers, which support stacked configuration. However, it's important to highlight certain aspects of these configurations. In parallel mode, each byte of data is stored in both flash devices, and the QSPI controller automatically handles the byte split and the simultaneous assertion/de-assertion of multiple CS lines. Hence, it can be stated that parallel operation is a controller feature, and other controllers wishing to operate flashes in parallel mode should be capable of data splitting and asserting multiple CS lines simultaneously. This characteristic might be specific to the AMD-Xilinx controller. In contrast, in stacked mode, only one CS pin is asserted at any given time, determined by the memory address and the accessed data length. Stacked mode, unlike parallel mode, functions as a software abstraction. Once implemented, any SPI controller with multiple CS lines or with a combination of native-CS and GPIO-CS can operate two or more flashes in stacked mode. > you also need to modify the spi controller and intercept some commands. Command interception occurs exclusively in parallel mode, not in stacked mode. In parallel mode, data must be split during flash memory read/write operations. However, during Flash register read/write operations, there should be no data split, as the identical data needs to be written to (or read from) the register of both flashes. Consequently, the driver has to intercept the command before activating the data split feature of the controller. > Can everything be moved there? In stacked mode, determining which flash device needs to be asserted is based on the flash address and the length of the requested data. This information is handled by the spi-nor core. If the operation spans across multiple flashes, the command, address, dummy (if required), and residual data must be issued to multiple flashes. This process should be carried out in the spi-nor core layer( or before spi-mem) and not in the driver. That is why > > I'm not sure we are implementing controller specific things in the core. Hard As explained earlier the parallel mode of operation can be controller specific, But the stacked mode is controller independent. > to judge without seeing other controllers doing a similar thing. I'd like to avoid > that. > > If we had some kind of abstraction here, that might be easier to adapt in the > future, but just putting everything into the core will make it really hard to > maintain. So if everything related to stacked and parallel memory would be in > drivers/mtd/spi-nor/stacked.c, we'd have at least everything in one place with > a proper interface between that and the core. I agree. Regards Amit > > -michael
----- Ursprüngliche Mail ----- > Von: "Amit Kumar Mahapatra" <amit.kumar-mahapatra@amd.com> > This patch series updated the spi-nor, spi core and the AMD-Xilinx GQSPI > driver to add stacked and parallel memories support. I wish the series had a real cover letter which explains the big picture in more detail. What I didn't really get so far, is it really necessary to support multiple chip selects within a single mtd? You changes introduce hard to maintain changes into the spi-nor/mtd core code which alert me. Why can't we have one mtd for each cs and, if needed, combine them later? We have drivers such as mtdconcat for reasons. Thanks, //richard
Hi Richard, richard@nod.at wrote on Mon, 18 Dec 2023 23:10:20 +0100 (CET): > ----- Ursprüngliche Mail ----- > > Von: "Amit Kumar Mahapatra" <amit.kumar-mahapatra@amd.com> > > > This patch series updated the spi-nor, spi core and the AMD-Xilinx GQSPI > > driver to add stacked and parallel memories support. > > I wish the series had a real cover letter which explains the big picture > in more detail. > > What I didn't really get so far, is it really necessary to support multiple > chip selects within a single mtd? > You changes introduce hard to maintain changes into the spi-nor/mtd core code > which alert me. > Why can't we have one mtd for each cs and, if needed, combine them later? > We have drivers such as mtdconcat for reasons. The Xilinx SPI controller is a bit convoluted, there are two ways to address the bits in a memory: * Either your extend the memory range with the second chip "on top" of the first (which would typically be a mtd-concat use case) * Or you use the two chips in parallel and you store the even bits in one device (let's say cs0) and the odd bits in the other (cs1). Extending mtd-concat for this might be another solution, I don't know how feasible it would be. Maybe these bindings will help understanding the logic: e2edd1b64f1c ("spi: dt-bindings: Describe stacked/parallel memories modes") eba5368503b4 ("spi: dt-bindings: Add an example with two stacked flashes") However I agree the changes will likely be hard to maintain given the complexity brought with such a different controller. Thanks, Miquèl