From patchwork Thu Apr 24 10:52:24 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicolin Chen X-Patchwork-Id: 4049181 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 7763D9F3E2 for ; Thu, 24 Apr 2014 10:51:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id ACBDC202EA for ; Thu, 24 Apr 2014 10:51:22 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 834A4202DD for ; Thu, 24 Apr 2014 10:51:21 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 6D71E265266; Thu, 24 Apr 2014 12:51:14 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,NO_DNS_FOR_FROM, UNPARSEABLE_RELAY autolearn=no version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id D28AB264F19; Thu, 24 Apr 2014 12:51:06 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id E6798265206; Thu, 24 Apr 2014 12:51:03 +0200 (CEST) Received: from na01-by2-obe.outbound.protection.outlook.com (mail-by2lp0240.outbound.protection.outlook.com [207.46.163.240]) by alsa0.perex.cz (Postfix) with ESMTP id 447D2261B2D for ; Thu, 24 Apr 2014 12:50:55 +0200 (CEST) Received: from CH1PR03CA007.namprd03.prod.outlook.com (10.255.156.152) by BLUPR03MB020.namprd03.prod.outlook.com (10.255.208.42) with Microsoft SMTP Server (TLS) id 15.0.934.12; Thu, 24 Apr 2014 10:50:49 +0000 Received: from BL2FFO11FD015.protection.gbl (10.255.156.132) by CH1PR03CA007.outlook.office365.com (10.255.156.152) with Microsoft SMTP Server (TLS) id 15.0.929.12 via Frontend Transport; Thu, 24 Apr 2014 10:50:49 +0000 Received: from az84smr01.freescale.net (192.88.158.246) by BL2FFO11FD015.mail.protection.outlook.com (10.173.160.223) with Microsoft SMTP Server (TLS) id 15.0.929.8 via Frontend Transport; Thu, 24 Apr 2014 10:50:49 +0000 Received: from rio.ap.freescale.net (rio.ap.freescale.net [10.192.242.9]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s3OAohpH002517; Thu, 24 Apr 2014 03:50:43 -0700 From: Nicolin Chen To: Date: Thu, 24 Apr 2014 18:52:24 +0800 Message-ID: <1398336744-4836-1-git-send-email-Guangyu.Chen@freescale.com> X-Mailer: git-send-email 1.8.4 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.246; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009001)(6009001)(428001)(189002)(199002)(46102001)(6806004)(76482001)(89996001)(31966008)(79102001)(85852003)(83072002)(74662001)(74502001)(48376002)(77096999)(87936001)(80976001)(36756003)(87286001)(50986999)(44976005)(4396001)(50226001)(50466002)(47776003)(77156001)(83322001)(80022001)(19580405001)(81342001)(19580395003)(99396002)(88136002)(81542001)(20776003)(92726001)(77982001)(62966002)(86362001)(92566001)(93916002); DIR:OUT; SFP:1101; SCL:1; SRVR:BLUPR03MB020; H:az84smr01.freescale.net; FPR:; MLV:sfv; PTR:gate-az5.freescale.com; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Exchange-Antispam-Report-Test: BL:0; ACTION:Default; RISK:Low; SCL:0; SPMLVL:NotSpam; PCL:0; RULEID: X-Forefront-PRVS: 01917B1794 Received-SPF: None (: freescale.com does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 192.88.158.246) smtp.mailfrom=guangyu.chen@freescale.com; X-OriginatorOrg: freescale.com Cc: tiwai@suse.de, alsa-devel@alsa-project.org, lgirdwood@gmail.com Subject: [alsa-devel] [PATCH] ASoC: fsl_spdif: Add core clock control for DMA access X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP Regmap is able to enable/disable the core clock automatically each time it's going to access the registers. But for DMA cases during playback or recording, it's totally beyong control of regmap. So we have to open the clock manually. Signed-off-by: Nicolin Chen --- sound/soc/fsl/fsl_spdif.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c index daa6198..e2836b3 100644 --- a/sound/soc/fsl/fsl_spdif.c +++ b/sound/soc/fsl/fsl_spdif.c @@ -80,6 +80,7 @@ struct fsl_spdif_priv { u8 rxclk_src; struct clk *txclk[SPDIF_TXRATE_MAX]; struct clk *rxclk; + struct clk *coreclk; struct snd_dmaengine_dai_dma_data dma_params_tx; struct snd_dmaengine_dai_dma_data dma_params_rx; @@ -423,10 +424,16 @@ static int fsl_spdif_startup(struct snd_pcm_substream *substream, /* Reset module and interrupts only for first initialization */ if (!cpu_dai->active) { + ret = clk_prepare_enable(spdif_priv->coreclk); + if (ret) { + dev_err(&pdev->dev, "failed to enable core clock\n"); + return ret; + } + ret = spdif_softreset(spdif_priv); if (ret) { dev_err(&pdev->dev, "failed to soft reset\n"); - return ret; + goto err; } /* Disable all the interrupts */ @@ -454,6 +461,11 @@ static int fsl_spdif_startup(struct snd_pcm_substream *substream, regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, 0); return 0; + +err: + clk_disable_unprepare(spdif_priv->coreclk); + + return ret; } static void fsl_spdif_shutdown(struct snd_pcm_substream *substream, @@ -484,6 +496,7 @@ static void fsl_spdif_shutdown(struct snd_pcm_substream *substream, spdif_intr_status_clear(spdif_priv); regmap_update_bits(regmap, REG_SPDIF_SCR, SCR_LOW_POWER, SCR_LOW_POWER); + clk_disable_unprepare(spdif_priv->coreclk); } } @@ -1134,6 +1147,13 @@ static int fsl_spdif_probe(struct platform_device *pdev) return ret; } + /* Get core clock for data register access via DMA */ + spdif_priv->coreclk = devm_clk_get(&pdev->dev, "core"); + if (IS_ERR(spdif_priv->coreclk)) { + dev_err(&pdev->dev, "no core clock in devicetree\n"); + return PTR_ERR(spdif_priv->coreclk); + } + /* Select clock source for rx/tx clock */ spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1"); if (IS_ERR(spdif_priv->rxclk)) {