From patchwork Tue May 27 08:24:23 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Pargmann X-Patchwork-Id: 4247801 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B34B79F1E7 for ; Tue, 27 May 2014 08:25:51 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B7F7420279 for ; Tue, 27 May 2014 08:25:50 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 523FC2026F for ; Tue, 27 May 2014 08:25:49 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 67020265795; Tue, 27 May 2014 10:25:48 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id 0E9262655A6; Tue, 27 May 2014 10:25:14 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 23873265594; Tue, 27 May 2014 10:25:13 +0200 (CEST) Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [92.198.50.35]) by alsa0.perex.cz (Postfix) with ESMTP id 5169E265521 for ; Tue, 27 May 2014 10:24:58 +0200 (CEST) Received: from dude.hi.pengutronix.de ([2001:6f8:1178:2:a236:9fff:fe00:814]) by metis.ext.pengutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1WpCgP-0007ER-3p; Tue, 27 May 2014 10:24:29 +0200 Received: from mpa by dude.hi.pengutronix.de with local (Exim 4.82) (envelope-from ) id 1WpCgV-0005lS-9g; Tue, 27 May 2014 10:24:35 +0200 From: Markus Pargmann To: Mark Brown Date: Tue, 27 May 2014 10:24:23 +0200 Message-Id: <1401179065-31195-7-git-send-email-mpa@pengutronix.de> X-Mailer: git-send-email 2.0.0.rc2 In-Reply-To: <1401179065-31195-1-git-send-email-mpa@pengutronix.de> References: <1401179065-31195-1-git-send-email-mpa@pengutronix.de> X-SA-Exim-Connect-IP: 2001:6f8:1178:2:a236:9fff:fe00:814 X-SA-Exim-Mail-From: mpa@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: alsa-devel@alsa-project.org Cc: Fabio Estevam , alsa-devel@alsa-project.org, Alexander Shiyan , Timur Tabi , "Li.Xiubo@freescale.com" , kernel@pengutronix.de, Nicolin Chen , Markus Pargmann , linux-arm-kernel@lists.infradead.org Subject: [alsa-devel] [PATCH v5 6/8] ASoC: fsl-ssi: Fix baudclock handling X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP The baudclock may be used and set by different streams. Allow only the first stream to set the bitclock rate. Other streams have to try to get to the correct rate without modifying the bitclock rate using the SSI internal clock modifiers. The variable baudclk_streams is introduced to keep track of the active streams that are using the baudclock. This way we know if the baudclock may be set and whether we may enable/disable the clock. baudclock enable/disable is moved to hw_params()/hw_free(). This way we can keep track of the baudclock in those two functions and avoid a running clock while it is not used. As hw_params()/hw_free() may be called multiple times for the same stream, we have to use baudclk_streams variable to know whether we may enable/disable the clock. Signed-off-by: Markus Pargmann Tested-By: Michael Grzeschik --- Notes: Changes in v5: - Moved fsl_ssi_is_i2s_master to a previous patch because of build issues sound/soc/fsl/fsl_ssi.c | 62 ++++++++++++++++++++++++++++++++----------------- 1 file changed, 41 insertions(+), 21 deletions(-) diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c index dbcde10..ac78660 100644 --- a/sound/soc/fsl/fsl_ssi.c +++ b/sound/soc/fsl/fsl_ssi.c @@ -160,11 +160,11 @@ struct fsl_ssi_private { unsigned int dai_fmt; bool use_dma; - bool baudclk_locked; bool use_dual_fifo; u8 i2s_mode; struct clk *baudclk; struct clk *clk; + unsigned int baudclk_streams; unsigned int bitclk_freq; struct snd_dmaengine_dai_dma_data dma_params_tx; struct snd_dmaengine_dai_dma_data dma_params_rx; @@ -495,9 +495,6 @@ static int fsl_ssi_startup(struct snd_pcm_substream *substream, struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai); - if (!dai->active && !fsl_ssi_is_ac97(ssi_private)) - ssi_private->baudclk_locked = false; - /* When using dual fifo mode, it is safer to ensure an even period * size. If appearing to an odd number while DMA always starts its * task from fifo0, fifo1 would be neglected at the end of each @@ -530,6 +527,7 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, unsigned long clkrate, baudrate, tmprate; u64 sub, savesub = 100000; unsigned int freq; + bool baudclk_is_used; /* Prefer the explicitly set bitclock frequency */ if (ssi_private->bitclk_freq) @@ -541,6 +539,8 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, if (IS_ERR(ssi_private->baudclk)) return -EINVAL; + baudclk_is_used = ssi_private->baudclk_streams & ~(BIT(substream->stream)); + /* It should be already enough to divide clock by setting pm alone */ psr = 0; div2 = 0; @@ -553,7 +553,11 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, continue; tmprate = freq * factor * (i + 2); - clkrate = clk_round_rate(ssi_private->baudclk, tmprate); + + if (baudclk_is_used) + clkrate = clk_get_rate(ssi_private->baudclk); + else + clkrate = clk_round_rate(ssi_private->baudclk, tmprate); do_div(clkrate, factor); afreq = (u32)clkrate / (i + 1); @@ -598,13 +602,12 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream, else write_ssi_mask(&ssi->srccr, mask, stccr); - if (!ssi_private->baudclk_locked) { + if (!baudclk_is_used) { ret = clk_set_rate(ssi_private->baudclk, baudrate); if (ret) { dev_err(cpu_dai->dev, "failed to set baudclk rate\n"); return -EINVAL; } - ssi_private->baudclk_locked = true; } return 0; @@ -656,6 +659,15 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, ret = fsl_ssi_set_bclk(substream, cpu_dai, hw_params); if (ret) return ret; + + /* Do not enable the clock if it is already enabled */ + if (!(ssi_private->baudclk_streams & BIT(substream->stream))) { + ret = clk_prepare_enable(ssi_private->baudclk); + if (ret) + return ret; + + ssi_private->baudclk_streams |= BIT(substream->stream); + } } /* @@ -683,6 +695,22 @@ static int fsl_ssi_hw_params(struct snd_pcm_substream *substream, return 0; } +static int fsl_ssi_hw_free(struct snd_pcm_substream *substream, + struct snd_soc_dai *cpu_dai) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct fsl_ssi_private *ssi_private = + snd_soc_dai_get_drvdata(rtd->cpu_dai); + + if (fsl_ssi_is_i2s_master(ssi_private) && + ssi_private->baudclk_streams & BIT(substream->stream)) { + clk_disable_unprepare(ssi_private->baudclk); + ssi_private->baudclk_streams &= ~BIT(substream->stream); + } + + return 0; +} + static int _fsl_ssi_set_dai_fmt(struct fsl_ssi_private *ssi_private, unsigned int fmt) { @@ -692,6 +720,11 @@ static int _fsl_ssi_set_dai_fmt(struct fsl_ssi_private *ssi_private, ssi_private->dai_fmt = fmt; + if (fsl_ssi_is_i2s_master(ssi_private) && IS_ERR(ssi_private->baudclk)) { + dev_err(&ssi_private->pdev->dev, "baudclk is missing which is necessary for master mode\n"); + return -EINVAL; + } + fsl_ssi_setup_reg_vals(ssi_private); scr = read_ssi(&ssi->scr) & ~(CCSR_SSI_SCR_SYN | CCSR_SSI_SCR_I2S_MODE_MASK); @@ -912,11 +945,6 @@ static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd, fsl_ssi_tx_config(ssi_private, false); else fsl_ssi_rx_config(ssi_private, false); - - if (!fsl_ssi_is_ac97(ssi_private) && (read_ssi(&ssi->scr) & - (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0) - ssi_private->baudclk_locked = false; - break; default: @@ -948,6 +976,7 @@ static int fsl_ssi_dai_probe(struct snd_soc_dai *dai) static const struct snd_soc_dai_ops fsl_ssi_dai_ops = { .startup = fsl_ssi_startup, .hw_params = fsl_ssi_hw_params, + .hw_free = fsl_ssi_hw_free, .set_fmt = fsl_ssi_set_dai_fmt, .set_sysclk = fsl_ssi_set_dai_sysclk, .set_tdm_slot = fsl_ssi_set_dai_tdm_slot, @@ -1087,8 +1116,6 @@ static int fsl_ssi_imx_probe(struct platform_device *pdev, if (IS_ERR(ssi_private->baudclk)) dev_dbg(&pdev->dev, "could not get baud clock: %ld\n", PTR_ERR(ssi_private->baudclk)); - else - clk_prepare_enable(ssi_private->baudclk); /* * We have burstsize be "fifo_depth - 2" to match the SSI @@ -1139,9 +1166,6 @@ static int fsl_ssi_imx_probe(struct platform_device *pdev, return 0; error_pcm: - if (!IS_ERR(ssi_private->baudclk)) - clk_disable_unprepare(ssi_private->baudclk); - clk_disable_unprepare(ssi_private->clk); return ret; @@ -1152,8 +1176,6 @@ static void fsl_ssi_imx_clean(struct platform_device *pdev, { if (!ssi_private->use_dma) imx_pcm_fiq_exit(pdev); - if (!IS_ERR(ssi_private->baudclk)) - clk_disable_unprepare(ssi_private->baudclk); clk_disable_unprepare(ssi_private->clk); } @@ -1248,8 +1270,6 @@ static int fsl_ssi_probe(struct platform_device *pdev) /* Older 8610 DTs didn't have the fifo-depth property */ ssi_private->fifo_depth = 8; - ssi_private->baudclk_locked = false; - dev_set_drvdata(&pdev->dev, ssi_private); if (ssi_private->soc->imx) {