diff mbox

ASoC: fsl_sai: Initialize with software reset

Message ID 1407230421-20953-1-git-send-email-nicoleotsuka@gmail.com (mailing list archive)
State Accepted
Commit 376d1a92ca587d3974d4791cdb99baa8b8e7f0dd
Headers show

Commit Message

Nicolin Chen Aug. 5, 2014, 9:20 a.m. UTC 
This patch adds software reset code in dai_probe() so as to make a true init
by clearing SAI's internal logic, including the bit clock generation, status
flags, and FIFO pointers.

Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
---
 sound/soc/fsl/fsl_sai.c | 9 +++++++--
 sound/soc/fsl/fsl_sai.h | 1 +
 2 files changed, 8 insertions(+), 2 deletions(-)

Comments

Mark Brown Aug. 7, 2014, 9:38 a.m. UTC | #1 
On Tue, Aug 05, 2014 at 05:20:21PM +0800, Nicolin Chen wrote:
> This patch adds software reset code in dai_probe() so as to make a true init
> by clearing SAI's internal logic, including the bit clock generation, status
> flags, and FIFO pointers.

Applied, thanks.
diff mbox

Patch

diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index dc84f98..ef7c758 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -438,8 +438,13 @@  static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
 {
 	struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
 
-	regmap_update_bits(sai->regmap, FSL_SAI_TCSR, 0xffffffff, 0x0);
-	regmap_update_bits(sai->regmap, FSL_SAI_RCSR, 0xffffffff, 0x0);
+	/* Software Reset for both Tx and Rx */
+	regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
+	regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
+	/* Clear SR bit to finish the reset */
+	regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
+	regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
+
 	regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
 			   FSL_SAI_MAXBURST_TX * 2);
 	regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index c24d3fd..b3d8864 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -48,6 +48,7 @@ 
 /* SAI Transmit/Recieve Control Register */
 #define FSL_SAI_CSR_TERE	BIT(31)
 #define FSL_SAI_CSR_FR		BIT(25)
+#define FSL_SAI_CSR_SR		BIT(24)
 #define FSL_SAI_CSR_xF_SHIFT	16
 #define FSL_SAI_CSR_xF_W_SHIFT	18
 #define FSL_SAI_CSR_xF_MASK	(0x1f << FSL_SAI_CSR_xF_SHIFT)