From patchwork Wed Sep 10 13:46:49 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Lavnikevich X-Patchwork-Id: 4877671 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id A2A12C0338 for ; Wed, 10 Sep 2014 13:59:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 009F5201D5 for ; Wed, 10 Sep 2014 13:59:33 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 0122820149 for ; Wed, 10 Sep 2014 13:59:28 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id D01AB265605; Wed, 10 Sep 2014 15:59:26 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id 4ED28265550; Wed, 10 Sep 2014 15:56:57 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 0858F265523; Wed, 10 Sep 2014 15:51:05 +0200 (CEST) Received: from s250.sam-solutions.net (s250.sam-solutions.net [217.21.49.219]) by alsa0.perex.cz (Postfix) with ESMTP id 08E8B26550E for ; Wed, 10 Sep 2014 15:50:57 +0200 (CEST) Received: from s326.sam-solutions.net ([217.21.35.11]) by s250.sam-solutions.net with esmtps (TLSv1:AES256-SHA:256) (Exim 4.77) (envelope-from ) id 1XRiIO-0000x9-0F; Wed, 10 Sep 2014 16:50:52 +0300 Received: from localhost (192.168.117.165) by S326.sam-solutions.net (217.21.35.11) with Microsoft SMTP Server (TLS) id 15.0.847.32; Wed, 10 Sep 2014 16:50:33 +0300 From: Dmitry Lavnikevich To: , , , , , , , , , , , , , Date: Wed, 10 Sep 2014 16:46:49 +0300 Message-ID: <1410356809-26179-6-git-send-email-d.lavnikevich@sam-solutions.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1410356809-26179-1-git-send-email-d.lavnikevich@sam-solutions.com> References: <1410356809-26179-1-git-send-email-d.lavnikevich@sam-solutions.com> MIME-Version: 1.0 X-Originating-IP: [192.168.117.165] X-ClientProxiedBy: S326.sam-solutions.net (217.21.35.11) To S326.sam-solutions.net (217.21.35.11) X-Mailman-Approved-At: Wed, 10 Sep 2014 15:56:53 +0200 Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, Dmitry Lavnikevich , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [alsa-devel] [PATCH 5/5] ASoC: tlv320aic3x: fix PLL D configuration X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP Current caching implementation during regcache_sync() call bypasses all register writes of values that are already known as default (regmap reg_defaults). Same time in TLV320AIC3x codecs register 5 (AIC3X_PLL_PROGC_REG) write should be immediately followed by register 6 write (AIC3X_PLL_PROGD_REG) even if it was not changed. Otherwise both registers will not be written. This brings to issue that appears particulary in case of 44.1kHz playback with 19.2MHz master clock. In this case AIC3X_PLL_PROGC_REG is 0x6e while AIC3X_PLL_PROGD_REG is 0x0 (same as register default). Thus AIC3X_PLL_PROGC_REG also remains not written and we get wrong playback speed. In this patch snd_soc_read() is used to get cached pll values and snd_soc_write() (unlike regcache_sync() this function doesn't bypasses hardware default values) to write them to registers. Signed-off-by: Dmitry Lavnikevich --- sound/soc/codecs/tlv320aic3x.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c index 64f179ee9834..5e8626ae612b 100644 --- a/sound/soc/codecs/tlv320aic3x.c +++ b/sound/soc/codecs/tlv320aic3x.c @@ -1121,6 +1121,7 @@ static int aic3x_regulator_event(struct notifier_block *nb, static int aic3x_set_power(struct snd_soc_codec *codec, int power) { struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); + unsigned int pll_c, pll_d; int ret; if (power) { @@ -1138,6 +1139,18 @@ static int aic3x_set_power(struct snd_soc_codec *codec, int power) /* Sync reg_cache with the hardware */ regcache_cache_only(aic3x->regmap, false); regcache_sync(aic3x->regmap); + + /* Rewrite paired PLL D registers in case cached sync skipped + * writing one of them and thus caused other one also not + * being written + */ + pll_c = snd_soc_read(codec, AIC3X_PLL_PROGC_REG); + pll_d = snd_soc_read(codec, AIC3X_PLL_PROGD_REG); + if (pll_c == aic3x_reg[AIC3X_PLL_PROGC_REG].def || + pll_d == aic3x_reg[AIC3X_PLL_PROGD_REG].def) { + snd_soc_write(codec, AIC3X_PLL_PROGC_REG, pll_c); + snd_soc_write(codec, AIC3X_PLL_PROGD_REG, pll_d); + } } else { /* * Do soft reset to this codec instance in order to clear