From patchwork Thu Oct 30 10:51:51 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 5197051 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id DBFF6C11AC for ; Thu, 30 Oct 2014 11:41:25 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 152AE2021B for ; Thu, 30 Oct 2014 11:41:25 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id CF88020138 for ; Thu, 30 Oct 2014 11:41:23 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id AFFC5265876; Thu, 30 Oct 2014 12:41:22 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id 03E7326549C; Thu, 30 Oct 2014 12:35:31 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id CE77B265767; Thu, 30 Oct 2014 12:35:28 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by alsa0.perex.cz (Postfix) with ESMTP id 009C02654B8 for ; Thu, 30 Oct 2014 12:32:49 +0100 (CET) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga102.fm.intel.com with ESMTP; 30 Oct 2014 04:32:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.97,862,1389772800"; d="scan'208";a="408441410" Received: from vkoul-udesk3.iind.intel.com (HELO localhost.localdomain) ([10.223.96.11]) by FMSMGA003.fm.intel.com with ESMTP; 30 Oct 2014 04:24:38 -0700 From: Vinod Koul To: alsa-devel@alsa-project.org Date: Thu, 30 Oct 2014 16:21:51 +0530 Message-Id: <1414666312-4657-9-git-send-email-vinod.koul@intel.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1414666312-4657-1-git-send-email-vinod.koul@intel.com> References: <1414666312-4657-1-git-send-email-vinod.koul@intel.com> Cc: Vinod Koul , broonie@kernel.org, subhransu.s.prusty@intel.com, lgirdwood@gmail.com Subject: [alsa-devel] [PATCH 8/9] ASoC: Intel: add shim save context and restore routines X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP From: Subhransu S. Prusty Some ACPI platform require the driver to save the shim register content and restore them after resume, so add the routines for these The APCI patch will use these routines Signed-off-by: Subhransu S. Prusty Signed-off-by: Vinod Koul --- sound/soc/intel/sst/sst.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 42 insertions(+), 0 deletions(-) diff --git a/sound/soc/intel/sst/sst.c b/sound/soc/intel/sst/sst.c index 97c737a..82346a0 100644 --- a/sound/soc/intel/sst/sst.c +++ b/sound/soc/intel/sst/sst.c @@ -329,7 +329,49 @@ void sst_configure_runtime_pm(struct intel_sst_drv *ctx) pm_runtime_put_noidle(ctx->dev); } +inline void sst_save_shim64(struct intel_sst_drv *ctx, + void __iomem *shim, + struct sst_shim_regs64 *shim_regs) +{ + unsigned long irq_flags; + + spin_lock_irqsave(&ctx->ipc_spin_lock, irq_flags); + + shim_regs->csr = sst_shim_read64(shim, SST_CSR), + shim_regs->pisr = sst_shim_read64(shim, SST_PISR), + shim_regs->pimr = sst_shim_read64(shim, SST_PIMR), + shim_regs->isrx = sst_shim_read64(shim, SST_ISRX), + shim_regs->isrd = sst_shim_read64(shim, SST_ISRD), + shim_regs->imrx = sst_shim_read64(shim, SST_IMRX), + shim_regs->imrd = sst_shim_read64(shim, SST_IMRD), + shim_regs->ipcx = sst_shim_read64(shim, ctx->ipc_reg.ipcx), + shim_regs->ipcd = sst_shim_read64(shim, ctx->ipc_reg.ipcd), + shim_regs->isrsc = sst_shim_read64(shim, SST_ISRSC), + shim_regs->isrlpesc = sst_shim_read64(shim, SST_ISRLPESC), + shim_regs->imrsc = sst_shim_read64(shim, SST_IMRSC), + shim_regs->imrlpesc = sst_shim_read64(shim, SST_IMRLPESC), + shim_regs->ipcsc = sst_shim_read64(shim, SST_IPCSC), + shim_regs->ipclpesc = sst_shim_read64(shim, SST_IPCLPESC), + shim_regs->clkctl = sst_shim_read64(shim, SST_CLKCTL), + shim_regs->csr2 = sst_shim_read64(shim, SST_CSR2); + + spin_unlock_irqrestore(&ctx->ipc_spin_lock, irq_flags); +} +static inline void sst_restore_shim64(struct intel_sst_drv *ctx, + void __iomem *shim, + struct sst_shim_regs64 *shim_regs) +{ + unsigned long irq_flags; + + /* + * we only need to restore IMRX for this case, rest will be + * initialize by FW or driver when firmware is loaded + */ + spin_lock_irqsave(&ctx->ipc_spin_lock, irq_flags); + sst_shim_write64(shim, SST_IMRX, shim_regs->imrx), + spin_unlock_irqrestore(&ctx->ipc_spin_lock, irq_flags); +} static int intel_sst_runtime_suspend(struct device *dev) {