From patchwork Mon Nov 3 18:28:56 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dylan Reid X-Patchwork-Id: 5219001 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 79F3B9F349 for ; Mon, 3 Nov 2014 18:30:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AC3662010B for ; Mon, 3 Nov 2014 18:30:16 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 72B7D20136 for ; Mon, 3 Nov 2014 18:30:15 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 7A86A2605E7; Mon, 3 Nov 2014 19:30:14 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,NO_DNS_FOR_FROM, RCVD_IN_DNSWL_NONE,UNPARSEABLE_RELAY autolearn=no version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id 35E46260553; Mon, 3 Nov 2014 19:29:33 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 6111126051A; Mon, 3 Nov 2014 19:29:30 +0100 (CET) Received: from mail-pa0-f73.google.com (mail-pa0-f73.google.com [209.85.220.73]) by alsa0.perex.cz (Postfix) with ESMTP id 18B9D2604F8 for ; Mon, 3 Nov 2014 19:29:21 +0100 (CET) Received: by mail-pa0-f73.google.com with SMTP id lj1so1978201pab.4 for ; Mon, 03 Nov 2014 10:29:20 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=FBe50+wjoXGETVMsPhpEgpGkvbOpKW32CA2AGQ7/o+k=; b=lb9OgUPQKAnCi0P8ttpU42WfF8WqkoraQmxz4oPmd+7pyARDhd1vhUpFctxqr8YGuB Ne5OQAEJFfRXz3ptjYiF/RzL6pBKWYaPB6zhrmx8PexFcK7Wj0ckJYo3sDPAxddsSz83 +/1PsTrs8v9dUV4qEnQzERFcG1SgTPe+RNC3P7zQ2pQc4JC3OPM84m4myST+o69zR6HX fcJTLemlloSOxopcrzmdd8AdO/OcLQTbieIdh+5mvwKt+tTc8LJkMc6iJdQQV9m+dP6o V2wAKrasI3CAtKPdf4zbXuXqyNE6TdsXy6gpIFTBdD9NRRKZb0qW+YSGTgOylXClRRhh 84zw== X-Gm-Message-State: ALoCoQkH5O0lVCSMybykcDHt0cRTcit/wv/TXkiSkhcTJQmeMryGqPK+Y7hk2yN99mO/vS0yPnMKvO9JWCuyT5e/6Lqb8HD6S7A5RRMskjYCdZwBKn9W8urNZiw6Q1FHQqFBEaJvecn5k+9Ax1DS9rd/ApHXNd4u2UO4ptD8xBYI1dizi6USGG8= X-Received: by 10.70.63.106 with SMTP id f10mr32875647pds.1.1415039360212; Mon, 03 Nov 2014 10:29:20 -0800 (PST) Received: from corpmail-nozzle1-1.hot.corp.google.com ([100.108.1.104]) by gmr-mx.google.com with ESMTPS id e24si970662yhe.3.2014.11.03.10.29.19 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Nov 2014 10:29:20 -0800 (PST) Received: from hojo20.mtv.corp.google.com ([172.22.65.103]) by corpmail-nozzle1-1.hot.corp.google.com with ESMTP id J1TuXOT5.1; Mon, 03 Nov 2014 10:29:20 -0800 Received: by hojo20.mtv.corp.google.com (Postfix, from userid 123195) id 2616E1C0880; Mon, 3 Nov 2014 10:29:19 -0800 (PST) From: Dylan Reid To: alsa-devel@alsa-project.org Date: Mon, 3 Nov 2014 10:28:56 -0800 Message-Id: <1415039337-28026-1-git-send-email-dgreid@chromium.org> X-Mailer: git-send-email 2.1.2.330.g565301e Cc: Dylan Reid , broonie@kernel.org, ralph.birt@maximintegrated.com, jerry.wong@maximintegrated.com Subject: [alsa-devel] [PATCH 1/2] ASoC: max98090: Correct pclk divisor settings X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP The Baytrail-based chromebooks have a 20MHz mclk, the code was setting the divisor incorrectly in this case. According to the 98090 datasheet, the divisor should be set to DIV1 for 10 <= mclk <= 20. Correct this and the surrounding clock ranges as well to match the datasheet. Signed-off-by: Dylan Reid --- sound/soc/codecs/max98090.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/sound/soc/codecs/max98090.c b/sound/soc/codecs/max98090.c index d519294..1229554 100644 --- a/sound/soc/codecs/max98090.c +++ b/sound/soc/codecs/max98090.c @@ -1941,13 +1941,13 @@ static int max98090_dai_set_sysclk(struct snd_soc_dai *dai, * 0x02 (when master clk is 20MHz to 40MHz).. * 0x03 (when master clk is 40MHz to 60MHz).. */ - if ((freq >= 10000000) && (freq < 20000000)) { + if ((freq >= 10000000) && (freq <= 20000000)) { snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, M98090_PSCLK_DIV1); - } else if ((freq >= 20000000) && (freq < 40000000)) { + } else if ((freq > 20000000) && (freq <= 40000000)) { snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, M98090_PSCLK_DIV2); - } else if ((freq >= 40000000) && (freq < 60000000)) { + } else if ((freq > 40000000) && (freq <= 60000000)) { snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, M98090_PSCLK_DIV4); } else {