From patchwork Thu Jan 8 12:12:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jie, Yang" X-Patchwork-Id: 5592291 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id C84CD9F357 for ; Thu, 8 Jan 2015 12:11:57 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 040C42038C for ; Thu, 8 Jan 2015 12:11:57 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id D475F20384 for ; Thu, 8 Jan 2015 12:11:54 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 97A6D260430; Thu, 8 Jan 2015 13:11:47 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id CA0F226041B; Thu, 8 Jan 2015 13:11:39 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 8687F260423; Thu, 8 Jan 2015 13:11:38 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by alsa0.perex.cz (Postfix) with ESMTP id 7C5FA260410 for ; Thu, 8 Jan 2015 13:11:31 +0100 (CET) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 08 Jan 2015 04:11:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.07,722,1413270000"; d="scan'208";a="658686395" Received: from keyon-u1310.sh.intel.com ([10.239.13.15]) by fmsmga002.fm.intel.com with ESMTP; 08 Jan 2015 04:11:22 -0800 From: Jie Yang To: broonie@kernel.org Date: Thu, 8 Jan 2015 20:12:52 +0800 Message-Id: <1420719172-28777-1-git-send-email-yang.jie@intel.com> X-Mailer: git-send-email 1.9.1 Cc: alsa-devel@alsa-project.org, liam.r.girdwood@intel.com Subject: [alsa-devel] [PATCH] ASoC: Intel: Always enable DRAM block for FW dump X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP The first 512 bytes of data DRAM memory is used for FW dump, and this first data SRAM block should be never power gated (always on), here always enable the block(DSRAM[0]) for D0 stage. Signed-off-by: Jie Yang --- sound/soc/intel/sst-haswell-dsp.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/sound/soc/intel/sst-haswell-dsp.c b/sound/soc/intel/sst-haswell-dsp.c index 57039b0..c42ffae 100644 --- a/sound/soc/intel/sst-haswell-dsp.c +++ b/sound/soc/intel/sst-haswell-dsp.c @@ -306,7 +306,7 @@ static void hsw_reset(struct sst_dsp *sst) static int hsw_set_dsp_D0(struct sst_dsp *sst) { int tries = 10; - u32 reg; + u32 reg, fw_dump_bit; /* Disable core clock gating (VDRTCTL2.DCLCGE = 0) */ reg = readl(sst->addr.pci_cfg + SST_VDRTCTL2); @@ -368,7 +368,9 @@ finish: can't be accessed, please enable each block before accessing. */ reg = readl(sst->addr.pci_cfg + SST_VDRTCTL0); reg |= SST_VDRTCL0_DSRAMPGE_MASK | SST_VDRTCL0_ISRAMPGE_MASK; - writel(reg, sst->addr.pci_cfg + SST_VDRTCTL0); + /* for D0, always enable the block(DSRAM[0]) used for FW dump */ + fw_dump_bit = 1 << SST_VDRTCL0_DSRAMPGE_SHIFT; + writel(reg & ~fw_dump_bit, sst->addr.pci_cfg + SST_VDRTCTL0); /* disable DMA finish function for SSP0 & SSP1 */ @@ -491,6 +493,7 @@ static const struct sst_sram_shift sram_shift[] = { {SST_DEV_ID_LYNX_POINT, 6, 16}, /* lp */ {SST_DEV_ID_WILDCAT_POINT, 2, 12}, /* wpt */ }; + static u32 hsw_block_get_bit(struct sst_mem_block *block) { u32 bit = 0, shift = 0, index; @@ -587,7 +590,9 @@ static int hsw_block_disable(struct sst_mem_block *block) val = readl(sst->addr.pci_cfg + SST_VDRTCTL0); bit = hsw_block_get_bit(block); - writel(val | bit, sst->addr.pci_cfg + SST_VDRTCTL0); + /* don't disable DSRAM[0], keep it always enable for FW dump*/ + if (bit != (1 << SST_VDRTCL0_DSRAMPGE_SHIFT)) + writel(val | bit, sst->addr.pci_cfg + SST_VDRTCTL0); /* wait 18 DSP clock ticks */ udelay(10); @@ -612,7 +617,7 @@ static int hsw_init(struct sst_dsp *sst, struct sst_pdata *pdata) const struct sst_adsp_memregion *region; struct device *dev; int ret = -ENODEV, i, j, region_count; - u32 offset, size; + u32 offset, size, fw_dump_bit; dev = sst->dma_dev; @@ -669,9 +674,11 @@ static int hsw_init(struct sst_dsp *sst, struct sst_pdata *pdata) } } + /* always enable the block(DSRAM[0]) used for FW dump */ + fw_dump_bit = 1 << SST_VDRTCL0_DSRAMPGE_SHIFT; /* set default power gating control, enable power gating control for all blocks. that is, can't be accessed, please enable each block before accessing. */ - writel(0xffffffff, sst->addr.pci_cfg + SST_VDRTCTL0); + writel(0xffffffff & ~fw_dump_bit, sst->addr.pci_cfg + SST_VDRTCTL0); return 0; }