From patchwork Mon Jan 19 21:24:28 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Thomas_Niederpr=C3=BCm?= X-Patchwork-Id: 5661161 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9205EC058D for ; Mon, 19 Jan 2015 21:23:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D09F720451 for ; Mon, 19 Jan 2015 21:23:34 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 935AE2041C for ; Mon, 19 Jan 2015 21:23:33 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id C1CC426152C; Mon, 19 Jan 2015 22:23:29 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,NO_DNS_FOR_FROM, UNPARSEABLE_RELAY autolearn=no version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id D8F20261528; Mon, 19 Jan 2015 22:23:21 +0100 (CET) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 93A1B261531; Mon, 19 Jan 2015 22:23:20 +0100 (CET) Received: from mailgw1.uni-kl.de (mailgw1.uni-kl.de [131.246.120.220]) by alsa0.perex.cz (Postfix) with ESMTP id ABED226150C for ; Mon, 19 Jan 2015 22:23:12 +0100 (CET) Received: from maestro.triple-a.uni-kl.de (vpn-ipv4-0737.triple-a.uni-kl.de [131.246.82.225]) by mailgw1.uni-kl.de (8.14.4/8.14.4/Debian-7) with ESMTP id t0JLN97f003301; Mon, 19 Jan 2015 22:23:10 +0100 From: =?UTF-8?q?Thomas=20Niederpr=C3=BCm?= To: peter.ujfalusi@ti.com, jarkko.nikula@bitmer.com Date: Mon, 19 Jan 2015 22:24:28 +0100 Message-Id: <1421702668-21135-1-git-send-email-niederp@physik.uni-kl.de> X-Mailer: git-send-email 2.1.1 MIME-Version: 1.0 Cc: alsa-devel@alsa-project.org, linux-omap@vger.kernel.org, =?UTF-8?q?Thomas=20Niederpr=C3=BCm?= Subject: [alsa-devel] [PATCH v2] ASoC: OMAP: mcbsp: ensure that CLKX and CLKR are not used as ouput pins when they are used as input clock for the SRG. X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP This patch fixes faulty behaviour in a setup where the input clock for the SRG is fed through the CLKR/CLKX pin but the McBSP is configured to be master (SND_SOC_DAIFMT_CBS_CFS). In that case of course CLKR/CLKX must not be configured as output pin. Otherwise the input clock is messed up horribly. This patch makes it possible to use the CLKR/CLKX pin rather than CLKS to inject a reference clock in setups where McBSP is master and not both rx and tx are used. However for this to work it has to be ensured that set_dai_sysclk() is called after set_dai_fmt(). This was tested on a beagleboard-xm using McBSP1 to drive a i2s DAC through the tx lines (CLKX,FSX,DX). Using this patch the CLKR pin is used to inject an external reference clock. changes since v1: - added comments explaining the bit masking to disable output on CLKR/CLKX Signed-off-by: Thomas Niederprüm Acked-by: Peter Ujfalusi --- sound/soc/omap/omap-mcbsp.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/sound/soc/omap/omap-mcbsp.c b/sound/soc/omap/omap-mcbsp.c index bd3ef2a..c37f606 100644 --- a/sound/soc/omap/omap-mcbsp.c +++ b/sound/soc/omap/omap-mcbsp.c @@ -530,8 +530,19 @@ static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai, case OMAP_MCBSP_SYSCLK_CLKX_EXT: regs->srgr2 |= CLKSM; + regs->pcr0 |= SCLKME; + /* + * If McBSP is master but yet the CLKX/CLKR pin drives the SRG, + * disable output on those pins. This enables to inject the + * reference clock through CLKX/CLKR. For this to work + * set_dai_sysclk() _needs_ to be called after set_dai_fmt(). + */ + regs->pcr0 &= ~CLKXM; + break; case OMAP_MCBSP_SYSCLK_CLKR_EXT: regs->pcr0 |= SCLKME; + /* Disable ouput on CLKR pin in master mode */ + regs->pcr0 &= ~CLKRM; break; default: err = -ENODEV;